Translated memory protection apparatus for an advanced microprocessor

• US 7,716,452 B1
• Filed: 05/13/2003
• Issued: 05/11/2010
• Est. Priority Date: 08/22/1996
• Status: Expired due to Term

• Current Assignee: Liberty Patents LLC
• Original Assignee: Intellectual Ventures Funding LLC (Intellectual Ventures LLC)
• Inventors: Wing, Malcolm J., Cmelik, Robert F., Kelly, Edmund J.
• Primary Examiner(s): Thai; Tuan V.
• Application Number:
  US10/438,158
• Time in Patent Office: 2,555 Days
• Field of Search: 714/9, 714/53, 714/723, 711/100, 711/147, 711/154, 711/200, 711/202, 711/203, 711/206, 711/207, 712/23, 712/204
• US Class Current: 711/206
• CPC Class Codes: G06F 13/4239 with asynchronous protocol
• CPC Class Codes: G06F 9/3808 for instruction reuse, e.g. trace cache, branch target cache
• CPC Class Codes: G06F 9/3812 with instruction modification, e.g. store into instruction stream
• CPC Class Codes: G06F 9/45504 Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators

Abstract

A method of responding to an attempt to write a memory address including a target instruction which has been translated to a host instruction for execution by a host processor including the steps of marking a memory address including a target instruction which has been translated to a host instruction, detecting a memory address which has been marked when an attempt is made to write to the memory address, and responding to the detection of a memory address which has been marked by protecting a target instruction at the memory address until it has been assured that translations associated with the memory address will not be utilized before being updated.

Claims

1. A host computer system for executing a target program, comprising:

a first primitive operation generated from a first target instruction in said target program;

a second primitive operation generated from a second target instruction in said target program; and

a translator scheduling said first primitive operation and said second primitive operation into an instruction of said host computer system and providing an indication that said first and second target instructions have been translated into said first and second primitive operations.

2. The host computer system of claim 1, wherein said first target instruction is compliant with an x-86 instruction set.

3. The host computer system of claim 1, wherein said second primitive operation is a speculative operation.

4. A method of executing a target program on a host computer system, said method comprising:

generating a first primitive operation from a first target instruction in said target program;

generating a second primitive operation from a second target instruction in said target program;

scheduling said first primitive operation and said second primitive operation into a host instruction of said host computer system;

providing an indication that said first and second target instructions have been translated into said first and second primitive operations; and

executing said host instruction.

5. The method of claim 4, wherein said first primitive operation is a speculative operation.

6. The method of claim 4, wherein said second primitive operation is a speculative operation.

7. A method of mapping host primitive operations generated from two target instructions into a host instruction during target program execution on host, said method comprising:

translating two target instructions into said host primitive operations;

scheduling said host primitive operations into said host instruction; and

indicating that said target instructions have been translated.

8. The method of claim 7, wherein at least one of said host primitive operations is a speculative operation.

9. A method of executing a target program on a host processor where the target and host instruction sets differ, the method comprising:

translating target instructions into host primitive operations;

mapping host primitive operations from two target instructions into a host instruction during target program execution on the host processor;

providing an indication that said target instructions have been translated; and

executing said host instruction.

10. The method of claim 9, wherein at least one of said host primitive operations is a speculative operation.

11. A method of executing a target program on a host processor where the target and host instruction sets differ, the method comprising:

translating target instructions into host primitive operations;

mapping a host primitive operation into a host instruction comprised of a host primitive operation translated from a different target instruction during target program execution on the host processor;

indicating that said target instructions have been translated; and

executing said host instruction.

12. The method of claim 11, wherein at least one of said host primitive operations is a speculative operation.

13. A method of executing a target program on a host processor where the target processor and host processor instruction sets differ, the method comprising:

storing state of said target processor as it exists at the beginning of translating a target instruction;

translating target instructions into one or more host instructions;

indicating that said target instructions have been translated;

storing said host instructions as a host translation in a buffer;

executing said host translation on said host processor; and

updating state of said host processor from stored state of said target processor if execution of said host translation generates an exception.

14. The method of claim 13, wherein said host translation is executed multiple times.

15. A method of executing a target program on a host processor, said method comprising:

storing a target processor state;

translating a plurality of target instructions into a host translation;

indicating that said target instructions have been translated;

storing said host translation in a buffer;

executing said host translation from said buffer;

generating an exception; and

restoring said target processor state.

16. A method of executing a target program comprising a sequence of a first target instruction followed by a second target instruction followed by a sub-sequence comprising at least one target instruction, said method comprising:

storing a target processor state after processing said first target instruction;

translating said second target instruction and said sub-sequence into a host translation;

indicating that said second target instruction has been translated;

storing said host translation in a buffer;

executing said host translation from said buffer;

generating an exception; and

restoring said target processor state.

17. A method of executing a target program on a host processor, said method comprising:

translating a plurality of target instructions into a host translation after storing a target processor state;

storing said host translation in a buffer;

indicating that said target instructions have been translated;

executing said host translation from said buffer;

generating an exception; and

restoring said target processor state.