Multi-CPU computer and method of restarting system

• US 7,716,520 B2
• Filed: 07/17/2007
• Issued: 05/11/2010
• Est. Priority Date: 02/07/2005
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Kondo, Hiroshi, Tabei, Ryo
• Primary Examiner(s): Maskulinski; Michael C
• Application Number:
  US11/879,390
• Publication Number:
  US 20080010506A1
• Time in Patent Office: 1,029 Days
• Field of Search: None
• US Class Current: 714/10
• CPC Class Codes: G06F 11/0724 in a multiprocessor or a multi-core unit multiprocessors per se G06F15/80
• CPC Class Codes: G06F 11/0775 Content or structure details of the error report, e.g. specific table structure, specific error fields
• CPC Class Codes: G06F 11/0778 Dumping, i.e. gathering error/state information after a fault for later diagnosis
• CPC Class Codes: G06F 11/0784 Routing of error reports, e.g. with a specific transmission path or data flow
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 11/1438 Restarting or rejuvenating

Abstract

A multi-CPU computer which is capable of positively performing error handling, and restarting a system even when a fatal error has occurred in a CPU. When a hardware error has occurred in a first CPU, error information is notified to a second CPU by a first error notification circuit of the first CPU. Then, the error information notified from the first CPU is obtained by a second error notification circuit of the second CPU, and error handling based on the error information is requested of an operating system. The second CPU executes a process for storing fault information including the error information in a storage device and a process for restarting the system, according to the operating system.

Claims

1. A multi-CPU computer system having a plurality of CPUs installed therein for operating on a common operating system, comprising:

a nonvolatile storage device;

a first CPU that incorporates a first error notification circuit for notifying another CPU of error information when a hardware error has occurred in said first CPU; and

a second CPU that incorporates a second error notification circuit for obtaining the error information from said first CPU and notifying the operating system of the error information, said second CPU executing a process for storing fault information including the error information in said storage device, and a process for restarting the multi-CPU computer system, according to the operating system, when the operating system is notified of the error information from said second error notification circuit;

wherein the first CPU further comprises a third error notification circuit to notify the operating system of the error information, and

wherein the first CPU temporarily stops processing according to the operating system upon notification of the error information by said third error notification circuit and, when the multi-CPU computer system is not restarted during the temporary stoppage of the processing, stores data including the error information in said nonvolatile storage device, and restarts the multi-CPU computer system according to the operating system after a lapse of a predetermined time period from the stoppage of the processing.

2. The multi-CPU computer system according to claim 1, further comprising a common memory having an inter-CPU communication area, wherein:

said first error notification circuit of said first CPU stores the error information in said inter-CPU communication area of said common memory; and

said second error notification circuit of said second CPU obtains the error information from said inter-CPU communication area.

3. A multi-CPU computer system comprising:

a nonvolatile storage device; and

a plurality of CPUs operating on a common operating system, each CPU comprising;

a first error notification circuit to notify another CPU of error information indicating a hardware error that has occurred locally, and

a second error notification circuit to notify the operating system of error information received from another CPU, and

a third error notification circuit to notify the operating system of the error information indicating the hardware error that has occurred locally;

wherein each CPU with the operating system is configured to execute;

storing, upon receipt of the error information by said second error notification circuit, fault information including the received error information said nonvolatile storage device and restarting the multi-CPU computer system according to the operating system,

stopping processing temporarily according to the operating system upon notification of the error information by said third error notification circuit, and

storing, when the multi-CPU computer system is not restarted during the temporary stoppage of the processing, data including the error information in said nonvolatile storage device, and restarting the multi-CPU computer system according to the operating system after a lapse of a predetermined time period from the stoppage of the processing.

4. A system-restarting method for a multi-CPU computer system that has a plurality of CPUs installed therein for operating on a common operating system, the method comprising:

sending, upon detection of a hardware error in a first CPU, error information indicating the detected hardware error from the first CPU to a second CPU;

sending the error information from the second CPU to the operating system;

storing, by the second CPU, fault information including the error information in a nonvolatile storage device, and restarting the multi-CPU computer system according to the operating system;

sending the error information from the first CPU to the operating system;

stopping processing in the first CPU temporarily according to the operating system; and

storing, by the first CPU when the multi-CPU computer system is not restarted during the temporary stoppage of the processing, data including the error information in said nonvolatile storage device, and restarting the multi-CPU computer system according to the operating system after a lapse of a predetermined time period from the stoppage of the processing.