Circuit for compression and storage of circuit diagnosis data
First Claim
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1. A circuit arrangement, comprising:
- an electronic circuit to be tested and/or diagnosed comprising a plurality of circuit inputs for receiving input data and a plurality of circuit outputs for supplying output data;
a compactor comprising;
test data inputs connected to the circuit outputs, test comparison inputs, and test data outputs; and
a memory device disposed on a semiconductor chip with the electronic circuit and the compactor, the memory device being configured to receive data supplied at the test data outputs of the compactor.
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Abstract
A compactor includes test data inputs that are connectable to circuit outputs of an electrical circuit, test comparison inputs, and test data outputs. The compactor further includes a number of H matrix XOR gates arranged as a switching mechanism between the test data inputs and the test data outputs such that data applied to the test data inputs is produced at the test data outputs compressed in accordance with coefficients of an H matrix of an error-correcting code, and compensation XOR gates arranged between the test data inputs and the test data outputs, each compensation XOR gate including an input for receiving a compensation value.
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Citations
17 Claims
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1. A circuit arrangement, comprising:
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an electronic circuit to be tested and/or diagnosed comprising a plurality of circuit inputs for receiving input data and a plurality of circuit outputs for supplying output data; a compactor comprising;
test data inputs connected to the circuit outputs, test comparison inputs, and test data outputs; anda memory device disposed on a semiconductor chip with the electronic circuit and the compactor, the memory device being configured to receive data supplied at the test data outputs of the compactor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A circuit arrangement, comprising:
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an electronic circuit to be tested and/or diagnosed comprising a plurality of circuit inputs for receiving input data and a plurality of circuit outputs for supplying output data; a compactor comprising;
test data inputs connected to the circuit outputs, test comparison inputs, and test data outputs;a memory device disposed on a semiconductor chip with the electronic circuit and the compactor, the memory device being configured to receive data supplied at the test data outputs of the compactor; a plurality of H matrix XOR gates arranged as a switching mechanism between the test data inputs and the test data outputs such that the data applied to the test data inputs is produced at the test data outputs compressed in accordance with coefficients of an H matrix of an error-correcting code; and compensation XOR gates arranged between the test data inputs and the test data outputs, each compensation XOR gate including an input for receiving a compensation value. - View Dependent Claims (12, 13, 14, 15, 16)
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17. A circuit arrangement, comprising:
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an electronic circuit to be tested and/or diagnosed comprising a plurality of circuit inputs for receiving input data and a plurality of circuit outputs for supplying output data; a compactor comprising;
test data inputs connected to the circuit outputs, test comparison inputs, and test data outputs, wherein at least some of the test data inputs of the compactor are connected to circuit outputs of the electronic circuit, which are outputs of scan paths; anda memory device disposed on a semiconductor chip with the electronic circuit and the compactor, the memory device being configured to receive data supplied at the test data outputs of the compactor.
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Specification