Semiconductor device, method for making pattern layout, method for making mask pattern, method for making layout, method for manufacturing photo mask, photo mask, and method for manufacturing semiconductor device

• US 7,716,617 B2
• Filed: 12/13/2005
• Issued: 05/11/2010
• Est. Priority Date: 12/13/2004
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Maesono, Atsushi, Mashita, Hiromitsu, Fujisawa, Tadahito, Kotani, Toshiya, Nakano, Ayako
• Primary Examiner(s): Kik; Phallaka
• Application Number:
  US11/299,843
• Publication Number:
  US 20060157833A1
• Time in Patent Office: 1,610 Days
• Field of Search: 326/41, 326/47, 326/101, 716/9, 716/10, 716/13, 716/14
• US Class Current: 716/119
• CPC Class Codes: G03F 1/00 Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
• CPC Class Codes: G03F 1/36 Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A semiconductor device includes a semiconductor substrate, and a circuit pattern group comprising at least N (≧2) circuit pattern on the semiconductor substrate, at least one vicinity of end portion among the at least of N circuit patterns including a connection area to electrically connect to a circuit pattern in another circuit pattern group different from the circuit pattern group, the at least N wirings pattern including a circuit pattern N1 and at least one circuit pattern Ni (i≧2) arranged in one direction different from longitudinal direction of the circuit pattern N1, the at least one circuit patterns Ni having larger i being arranged at further position away from the circuit pattern N1, and in terms of a pattern including the connection area among the at least of Ni circuit patterns, the larger the i, the connection area being arranged at a further position in longitudinal direction.

Claims

1. A semiconductor device comprising:

a semiconductor substrate; and

a circuit pattern group comprising at least N (N≧

2) pieces of circuit patterns provided on the semiconductor substrate,

at least one vicinity of end portion among the at least of N pieces of circuit patterns including a connection area to electrically connect to a circuit pattern in another circuit pattern group being different from the circuit pattern group,

the N pieces of circuit patterns including a circuit pattern N1 and at least one circuit pattern Ni (i≧

2) arranged in one direction being different from a longitudinal direction of the circuit pattern N1,

the at least one circuit pattern Ni having larger i being arranged at a further position away from the circuit pattern N1, and in terms of a pattern including the connection area among the at least of N pieces of circuit patterns, the larger the i, the connection area being arranged at a further position in the longitudinal direction.

2. The semiconductor device according to claim 1, wherein in each of circuit pattern Nj (j≧

1), width of the connection area is wider than that of the circuit pattern.

3. The semiconductor device according to claim 1, wherein the circuit pattern group further comprises a dummy pattern.

4. The semiconductor device according to claim 1, wherein

N pieces of the circuit patterns are arranged such that connection area of circuit pattern Nj (j≧

1) and the connection area of the circuit pattern Nj+1 does not overlap one another with respect to the one direction.

5. A method for making a pattern layout on a substrate, comprising:

defining a circuit pattern N1 as a reference for arranging N (N≧

2) pieces of circuit patterns in a first circuit pattern group, each of the N pieces of the circuit patterns including a connection area to electrically connect to a circuit pattern in a second circuit pattern group different from the first circuit pattern group, wherein the circuit pattern N1 belongs to the N pieces of the circuit patterns;

arranging at least one circuit pattern Ni (i≧

2) in one direction different from a longitudinal direction of the circuit pattern N1, the at least one circuit pattern Ni having larger i being arranged at a further position away from the circuit pattern N1, wherein the at least one circuit pattern Ni belongs to the N pieces of the circuit patterns;

enlarging the at least one circuit pattern Ni in the longitudinal direction, the at least one circuit pattern Ni having larger i being enlarged larger; and

forming the pattern layout onto the substrate.

6. The method for making a pattern layout according to claim 5, wherein in each of circuit patterns Nj (j≧

1), width of the connection area is wider than that of the circuit pattern.

7. The method for making a pattern layout according to claim 5, wherein the circuit pattern group further comprises a dummy pattern.

8. The method for making a pattern layout according to claim 7, wherein the dummy pattern includes a dummy pattern to be a subject of optical proximity correction, and a dummy pattern not to be a subject of optical proximity correction.

9. The method for making a pattern layout according to claim 7, wherein the dummy pattern includes a line &

space pattern and a large pattern including a dimension for defining size of the large pattern, and the dimension is larger than that of the line &

space pattern.