Tasks distribution in a multi-processor including a translation lookaside buffer shared between processors

• US 7,716,673 B2
• Filed: 07/31/2003
• Issued: 05/11/2010
• Est. Priority Date: 07/31/2002
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: D'Inverno, Dominique, Chauvel, Gerard
• Primary Examiner(s): An; Meng-Ai
• Assistant Examiner(s): To; Jennifer N
• Application Number:
  US10/632,077
• Publication Number:
  US 20040025161A1
• Time in Patent Office: 2,476 Days
• Field of Search: 718100-108, 718/1, 717/147, 711/118, 711/122, 711/207, 711/216, 711/145, 711/6, 711202-205, 712/43
• US Class Current: 718/108
• CPC Class Codes: G06F 12/0253 Garbage collection, i.e. reclamation of unreferenced memory
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 12/0891 using clearing, invalidating or resetting means
• CPC Class Codes: G06F 12/1036 for multiple virtual address spaces, e.g. segmentation G06F12/1045 takes precedence
• CPC Class Codes: G06F 12/126 with special data handling, e.g. priority of data or instructions, handling errors or pinning
• CPC Class Codes: G06F 2212/502 using adaptive policy
• CPC Class Codes: G06F 2212/681 Multi-level TLB, e.g. microTLB and main TLB
• CPC Class Codes: G06F 9/30174 for non-native instruction set, e.g. Javabyte, legacy code
• CPC Class Codes: G06F 9/3879 for non-native instruction execution, e.g. executing a command; for Java instruction set

Abstract

A system comprises a first processor, a second processor coupled to the first processor, an operating system that executes exclusively only on the first processor and not on the second processor, and a middle layer software running on the first processor and that distributes tasks to run on either or both processors. A synchronization unit coupled to the first and second processors also may be provided to synchronize the processors. Further still, a translation lookaside buffer may be included that is shared between the processors. Each entry in the translation lookaside buffer (“TLB”) may include a task identifier to permit the operating system or middle layer software to selectively flush only some of the TLB entries (e.g., the entries pertaining to only one of the processors).

Claims

1. A system comprising:

a first processor;

a second processor coupled to the first processor, and only the first processor configured to execute a single operating system, the second processor not executing an operating system;

a middle layer software configured to execute on the first processor and configured to distribute tasks to run on either or both processors; and

a shared translation lookaside buffer (TLB) configured to contain a plurality of entries in which virtual-to-physical address translations are stored, each entry also comprising a task ID field in which a task ID associated with the corresponding translation and with a task running on the first or second processor is stored, wherein at least one of the shared TLB entries are invalidated, and those entries that are invalidated have task IDs that are associated with tasks that are running or have run on only one of the first or second processors.

2. The system of claim 1 wherein the middle layer software comprises a Java virtual machine.

3. The system of claim 1 further comprising a synchronization unit coupled to the first and second processors, said synchronization unit configured to synchronize the execution of the first and second processors.

4. The system of claim 3 wherein the synchronization unit is configured to cause the first processor to transition to a wait mode while the second processor executes a task.

5. The system of claim 4 wherein the first processor is configured to transition from the wait mode to a fully operational mode by a signal asserted by the either the first or second processor to the synchronization unit.

6. The system of claim 1 wherein the operating system is configured to selectively flush at least one of the entries in the shared TLB based on task ID.

7. The system of claim 1 wherein the middle layer software is configured to selectively flush at least one of the entries in the shared TLB based on task ID.

8. The system of claim 7 wherein the middle layer software comprises a Java virtual machine.

9. The system of claim 1 wherein the second processor has a programmable context and is configured to autonomously switch its own context without support from the operating system executing on the first processor.

10. The system of claim 1 wherein the second processor includes a programmable task ID register which is configured to contain a value indicative of the task currently running on the second processor that is written by the middle layer software running on the first processor.

11. A method usable in a multi-processor system, comprising:

executing a single operating system in the multi-processor system, the single operating system executing on only one of a plurality of processors, the remaining ones of the plurality of processors not executing an operating system;

distributing tasks to each of the plurality of processors by middle layer software running on the processor on which the operating system executes, wherein each task has a unique task identifier value and the method further comprises writing virtual-to-physical address translations and task identifier values associated with the task to which the translations pertain into a translation lookaside buffer that is shared between the plurality of processors; and

selecting task identifier values and invalidating entries in the translation lookaside buffer that contain the selected task identifier values and not invalidating other entries in the translation lookaside buffer.

12. The method of claim 11 wherein distributing tasks comprises distributing tasks by a Java virtual machine.

13. The method of claim 11 further comprising causing the processor on which the operating system executes to transition to a wait mode while another processor executes tasks and subsequently transitioning the processor in the wait mode to an active mode as a result of a signal being asserted by any of the plurality of processors.

14. The method of claim 11 wherein, in a processor having a context and that does not execute the operating system, autonomously switching said context without support from the operating system.

15. The method of claim 11 further comprising writing a task ID register by the processor executing the operating system, the task ID register contained in another processor.