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Process of fabricating flash memory with enhanced program and erase coupling

  • US 7,718,488 B2
  • Filed: 04/27/2006
  • Issued: 05/18/2010
  • Est. Priority Date: 03/17/2004
  • Status: Active Grant
First Claim
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1. A process of fabricating a flash memory cell array, comprising the steps of:

  • forming a source diffusion between two bit line diffusions in a substrate,forming stacked pairs of control gates and floating gates on the substrate on opposite sides of the source diffusion, with each stacked pair having a control gate positioned above a floating gate,forming an erase gate on the substrate between the stacked pairs, andforming select gates on the substrate between the stacked pairs and the bit line diffusions,the erase gate and the select gates being formed by depositing a layer of silicon over, between and beside the stacked gates, and removing the portions of the silicon above the stacked gates and above the bit line diffusions.

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