Process of fabricating flash memory with enhanced program and erase coupling

• US 7,718,488 B2
• Filed: 04/27/2006
• Issued: 05/18/2010
• Est. Priority Date: 03/17/2004
• Status: Active Grant

• Current Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Original Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Inventors: Tuntasood, Prateep, Fan, Der-Tsyr, Chen, Chiou-Feng
• Primary Examiner(s): Smoot; Stephen W
• Assistant Examiner(s): Booker; Vicki B
• Application Number:
  US11/380,595
• Publication Number:
  US 20060203552A1
• Time in Patent Office: 1,482 Days
• Field of Search: 438/258, 438/257, 257/E27.103, 257/314, 257/315, 257/E21.68, 257/E21.681, 257/E29.3
• US Class Current: 438/257
• CPC Class Codes: G11C 16/0425 comprising cells containing a merged floating gate and select transistor
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Self-aligned split-gate flash memory cell array and process of fabrication in which erase and select gates are positioned on opposite sides of stacked floating and control gates, with source regions in the substrate beneath the erase gates, bit line diffusions which are partially overlapped by select gates at the ends of the rows of the cells. The floating and control gates are self-aligned with each other, and the erase and select gates are split from but self-aligned with the stacked gates. With the floating gates surrounded by the other gates and the source regions, high voltage coupling for both programming and erase operations is significantly enhanced. The memory cells are substantially smaller than prior art cells, and the array is biased so that all of the memory cells in it can be erased simultaneously, while programming is bit selectable.

Claims

1. A process of fabricating a flash memory cell array, comprising the steps of:

forming a source diffusion between two bit line diffusions in a substrate,

forming stacked pairs of control gates and floating gates on the substrate on opposite sides of the source diffusion, with each stacked pair having a control gate positioned above a floating gate,

forming an erase gate on the substrate between the stacked pairs, and

forming select gates on the substrate between the stacked pairs and the bit line diffusions,

the erase gate and the select gates being formed by depositing a layer of silicon over, between and beside the stacked gates, and removing the portions of the silicon above the stacked gates and above the bit line diffusions.

2. The process of claim 1 wherein the source diffusion is formed after the stacked pairs of control gates and floating gates are formed.

3. The process of claim 1 wherein the source diffusion is formed by ion implantation.

4. The process of claim 3 wherein the ion implantation is done with dopants selected from the group consisting of P³¹ and As⁷⁵.

5. The process of claim 1 wherein the bit line diffusions are formed after the select gates are formed.

6. The process of claim 1 wherein the bit line diffusions are formed by ion implantation.

7. The process of claim 6 wherein the ion implantation is done with dopants selected from the group consisting of P³¹ and As⁷⁵.

8. The process of claim 1 wherein the floating gates and the control gates are formed by

depositing a first layer of silicon on the substrate,

forming a second layer of silicon above the first layer,

removing portions of the second layer to form the control gates, and

removing portions of the first layer to form the floating gates.

9. The process of claim 8 wherein the portions of the first and second layers of silicon are removed by etching.

10. The process of claim 1 wherein the bit line diffusions are formed after the select gates are formed.

11. The process of claim 1 including the steps of forming a relatively thin tunnel oxide between the floating gates and the substrate, a first relatively thick dielectric between the floating gates and the select and erase gates, and a second relatively thick dielectric between floating gates and control gates.

12. The process of claim 1 including the steps of

forming relatively thin tunnel oxides between the each of the floating gates and the substrate,

forming a first relatively thick dielectric between the floating gates and the select and erase gates, and

forming a second relatively thick dielectric between the floating gate and the control gate in each pair of stacked gates.

13. The process of claim 1 including the steps of

forming bit line lines which cross over the stacked gates, the select gates, and the erase gate, and

forming bit line contacts which interconnect the bit line diffusions and the bit lines.

14. The process of claim 1 wherein the stacked gates and the source diffusion are formed in such manner that the floating gates partly overlie the source diffusion.

15. The process of claim 1 wherein the select gates and the bit line diffusions are formed in such manner that the select gates partly overlie the bit line diffusions.

16. A process of fabricating a flash memory cell, comprising the steps of:

forming a vertically stacked pair of floating and control gates on a silicon substrate by forming an oxide layer on an active area of the substrate, forming a first silicon layer on the oxide layer, etching away portions of the first silicon layer to form spaced apart rows of silicon which extend in a first direction on the substrate, forming a first dielectric film over the rows of silicon, forming a second silicon layer on the first dielectric film, forming a second dielectric film on the second silicon layer, etching away portions of the second dielectric film and the second silicon layer to form control gates with exposed side walls which extend in a direction perpendicular to the rows of silicon, and etching away portions of the rows of silicon and the first dielectric film to form floating gates which are stacked beneath and self-aligned with control gates;

forming a source diffusion in the active area on one side of the stacked pair;

forming a third dielectric film on the side walls of the control and floating gates and on the active area of the silicon substrate;

depositing a third silicon layer over the third dielectric film;

removing portions of the third silicon layer to form select and erase gates on opposite sides of the stacked gates, with the erase gate being positioned directly above the source diffusion;

forming a bit line diffusion in the active area of the substrate near the select gate;

forming a bit line which extends in the first direction above the gates; and

interconnecting the bit line and the bit line diffusion with a bit line contact.

17. The process of claim 16 including the steps of

forming a bit line which crosses above the vertically stacked pair, the erase gate and the select gate, and

forming a bit line contact which interconnects the bit line diffusion and the bit line.

18. The process of claim 16 including the steps of forming a relatively thin tunnel oxide between the floating gate and the substrate, a first relatively thick dielectric between the floating gate and the select and erase gates, and a second relatively thick dielectric between the floating gate and the control gate.

19. The process of claim 16 wherein

a second bit line diffusion is formed in the substrate,

the source diffusion is formed between the two bit line diffusions,

stacked pairs of control gates and floating gates are formed on the substrate on opposite sides of the source diffusion, with each stacked pair having a control gate positioned above a floating gate,

the erase gate is formed between the stacked pairs, and

select gates are formed between the stacked pairs and the bit line diffusions.

20. A process of fabricating a flash memory cell array, comprising the steps of:

forming an oxide layer on an active area in a silicon substrate,

forming a first silicon layer on the oxide layer,

forming a first dielectric film over the first silicon layer,

forming a second silicon layer on the first dielectric film,

forming a second dielectric film on the second silicon layer,

etching away portions of the second silicon layer and the second dielectric film to form control gates,

etching away portions of the first layer of silicon and the first dielectric film to form floating gates which are stacked beneath and self-aligned with control gates,

forming source regions in the active area between the stacked gates,

forming a third dielectric film on the side walls of the control and floating gates and on the active area of the silicon substrate,

depositing a third silicon layer over the third dielectric film,

removing portions of the third silicon layer to form select and erase gates on opposite sides of the stacked gates, with the erase gates being positioned directly above the source regions,

forming bit line diffusions in the active area of the substrate which are partially overlapped by the select gates,

forming bit line lines which extend above the gates, and

forming bit line contacts which interconnect the bit lines and the bit line diffusions.

21. A process of fabricating a flash memory cell array, comprising the steps of:

forming an oxide layer on an active area in a silicon substrate,

forming a first silicon layer on the oxide layer,

etching away portions of the first silicon layer to form spaced apart rows of silicon which extend in a first direction on the substrate,

forming a first dielectric film over the rows of silicon,

forming a second silicon layer on the first dielectric film,

forming a second dielectric film on the second silicon layer,

etching away portions of the second silicon layer and the second dielectric film to form control gates with exposed side walls which extend in a direction perpendicular to the rows of silicon,

etching away portions of the rows of silicon and the first dielectric film to form floating gates which are stacked beneath and self-aligned with control gates,

forming source regions in the active area of the substrate between the stacked gates,

forming a third dielectric film on the side walls of the control and floating gates and on the active area of the silicon substrate,

depositing a third silicon layer over the third dielectric film,

removing portions of the third silicon layer to form select and erase gates on opposite sides of the stacked gates, with the erase gates being positioned directly above the source regions,

forming bit line diffusions in the active area of the substrate which are partially overlapped by the select gates, and

forming bit line lines which extend in the first direction above the gates and bit line contacts which interconnect the bit lines and the bit line diffusions.