Methods of forming integrated circuitry, methods of forming memory circuitry, and methods of forming field effect transistors

• US 7,718,495 B2
• Filed: 09/04/2007
• Issued: 05/18/2010
• Est. Priority Date: 12/03/2004
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Parekh, Kunal R., Zahurak, John K.
• Primary Examiner(s): MENZ, LAURA MARY
• Application Number:
  US11/849,813
• Publication Number:
  US 20070298570A1
• Time in Patent Office: 987 Days
• Field of Search: 438/275, 438/595, 438/279
• US Class Current: 438/275
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/43 comprising only one type of peripheral transistor

Abstract

The invention includes methods of forming integrated circuitry, methods of forming memory circuitry, and methods of forming field effect transistors. In one implementation, conductive metal silicide is formed on some areas of a substrate and not on others. In one implementation, conductive metal silicide is formed on a transistor source/drain region and which is spaced from an anisotropically etched sidewall spacer proximate a gate of the transistor.

Claims

1. A method of forming integrated circuitry comprising:

providing a silicon-comprising substrate comprising a first circuitry area and a second circuitry area, the first circuitry area comprising a first pair of spaced adjacent gate electrodes received over the silicon-comprising substrate in at least a first cross-section of the substrate, spaced and facing anisotropically etched electrically insulative sidewall spacers being provided in the first cross-section between the gate electrodes of the first pair, the second circuitry area comprising a second pair of spaced adjacent gate electrodes received over the silicon-comprising substrate in at least a second cross-section of the substrate, spaced and facing anisotropically etched insulative sidewall spacers being provided in the second cross-section between the gate electrodes of the second pair, the facing anisotropically etched sidewall spacers between the second pair being spaced further from one another in the second cross-section than are those received between the first pair in the first cross-section;

depositing a masking material between the facing anisotropically etched sidewall spacers received between each of the first and second pairs of gate electrodes;

removing the masking material effective to expose silicon between the facing anisotropically etched sidewall spacers received between the second pair in the second cross-section but not between the facing anisotropically etched sidewall spacers received between the first pair in the first cross-section; and

after the removing, depositing metal over the substrate and annealing the substrate effective to react the metal with silicon of the substrate to form an electrically conductive metal silicide between the facing anisotropically etched sidewall spacers received between the second pair in the second cross-section but not between the facing anisotropically etched sidewall spacers received between the first pair in the first cross-section.

2. The method of claim 1 wherein the removing of the masking material is selective relative to the sidewall spacers.

3. The method of claim 1 wherein the first circuitry area comprises a memory array and the second circuitry area comprises peripheral circuitry to the memory array.

4. The method of claim 1 wherein the masking material comprises amorphous carbon.

5. The method of claim 1 wherein the masking material comprises transparent carbon.

6. The method of claim 1 wherein the masking material is semiconductive.

7. The method of claim 1 wherein the removing comprises chemical etching.

8. The method of claim 1 wherein said depositing metal and annealing the substrate occur simultaneously over at least some period of time.

9. The method of claim 1 wherein said depositing metal and annealing the substrate occur over at least some non-simultaneous periods of time.

10. The method of claim 1 comprising after said depositing metal and annealing, removing all of said masking material in the first cross-section.

11. The method of claim 1 comprising after said depositing metal and annealing, removing all of said masking material from the substrate.

12. The method of claim 1 wherein said removing of the masking material effective to expose silicon occurs without any photolithographic patterning within the first and second cross-sections.

13. The method of claim 1 wherein said removing of the masking material effective to expose silicon occurs without any photolithographic patterning anywhere on the substrate.

14. A method of forming integrated circuitry comprising:

providing a silicon-comprising substrate comprising a first circuitry area and a second circuitry area, the first circuitry area comprising a first pair of spaced adjacent gate electrodes received over the silicon-comprising substrate in at least a first cross-section of the substrate, spaced and facing anisotropically etched electrically insulative sidewall spacers being provided in the first cross-section between the gate electrodes of the first pair, the second circuitry area comprising a second pair of spaced adjacent gate electrodes received over the silicon-comprising substrate in at least a second cross-section of the substrate, spaced and facing anisotropically etched insulative sidewall spacers being provided in the second cross-section between the gate electrodes of the second pair, the facing anisotropically etched sidewall spacers between the second pair being spaced further from one another in the second cross-section than are those received between the first pair in the first cross-section;

depositing electrically insulative masking material between the facing anisotropically etched sidewall spacers received between each of the first and second pairs of gate electrodes;

removing the masking material effective to expose silicon between the facing anisotropically etched sidewall spacers received between the second pair in the second cross-section but not between the facing anisotropically etched sidewall spacers received between the first pair in the first cross-section; and

after the removing, depositing metal over the substrate and annealing the substrate effective to react the metal with silicon of the substrate to form an electrically conductive metal silicide between the facing anisotropically etched sidewall spacers received between the second pair in the second cross-section but not between the facing anisotropically etched sidewall spacers received between the first pair in the first cross-section.

15. The method of claim 14 wherein the masking material comprises silicon nitride.

16. The method of claim 14 wherein the masking material comprises silicon dioxide.

17. A method of forming integrated circuitry comprising:

providing a silicon-comprising substrate comprising a first circuitry area and a second circuitry area, the first circuitry area comprising a first pair of spaced adjacent gate electrodes received over the silicon-comprising substrate in at least a first cross-section of the substrate, spaced and facing anisotropically etched electrically insulative sidewall spacers being provided in the first cross-section between the gate electrodes of the first pair, the second circuitry area comprising a second pair of spaced adjacent gate electrodes received over the silicon-comprising substrate in at least a second cross-section of the substrate, spaced and facing anisotropically etched insulative sidewall spacers being provided in the second cross-section between the gate electrodes of the second pair, the facing anisotropically etched sidewall spacers between the second pair being spaced further from one another in the second cross-section than are those received between the first pair in the first cross-section;

depositing electrically conductive masking material between the facing anisotropically etched sidewall spacers received between each of the first and second pairs of gate electrodes;

removing the masking material effective to expose silicon between the facing anisotropically etched sidewall spacers received between the second pair in the second cross-section but not between the facing anisotropically etched sidewall spacers received between the first pair in the first cross-section; and

after the removing, depositing metal over the substrate and annealing the substrate effective to react the metal with silicon of the substrate to form an electrically conductive metal silicide between the facing anisotropically etched sidewall spacers received between the second pair in the second cross-section but not between the facing anisotropically etched sidewall spacers received between the first pair in the first cross-section.

18. The method of claim 17 wherein the masking material comprises a metal nitride.

19. The method of claim 18 wherein the masking material comprises tungsten nitride.

20. The method of claim 18 wherein the masking material comprises titanium nitride.