SOI device and method for its fabrication

• US 7,718,503 B2
• Filed: 07/21/2006
• Issued: 05/18/2010
• Est. Priority Date: 07/21/2006
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Wu, Donggang D., Pellela, Mario M., Buller, James F.
• Primary Examiner(s): Nguyen; Khiem D
• Application Number:
  US11/459,316
• Publication Number:
  US 20080017906A1
• Time in Patent Office: 1,397 Days
• Field of Search: 438/200, 438/237, 438/253, 438/396, 257/306, 257/347, 257/373, 257/E21.351, 257/E21.364
• US Class Current: 438/396
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688

Abstract

A silicon on insulator (SOI) device and methods for fabricating such a device are provided. The device includes an MOS capacitor coupled between voltage busses and formed in a monocrystalline semiconductor layer overlying an insulator layer and a semiconductor substrate. The device includes at least one electrical discharge path for discharging potentially harmful charge build up on the MOS capacitor. The MOS capacitor has a conductive electrode material forming a first plate of the MOS capacitor and an impurity doped region in the monocrystalline silicon layer beneath the conductive electrode material forming a second plate. A first voltage bus is coupled to the first plate of the capacitor and to an electrical discharge path through a diode formed in the semiconductor substrate and a second voltage bus is coupled to the second plate of the capacitor.

Claims

1. A method for fabricating a semiconductor on insulator (SOI) device comprising a semiconductor substrate, a buried insulator layer overlying the semiconductor substrate, and a monocrystalline semiconductor layer overlying the buried insulator layer, the method comprising the steps of:

forming a MOS capacitor coupled between a first voltage bus and a second voltage bus, the MOS capacitor having a gate electrode material forming a first plate of the MOS capacitor and coupled to the first voltage bus, an impurity doped region in the monocrystalline semiconductor layer beneath the gate electrode material forming a second plate of the MOS capacitor and coupled to the second voltage bus, a first contact region electrically in series with the impurity doped region, and a second contact region electrically in series with the impurity doped region, wherein the gate electrode material, impurity doped region, first contact region, and second contact region each have the same conductivity type;

forming a first electrical discharge path coupling the first plate of the MOS capacitor to a diode formed in the semiconductor substrate, wherein the first voltage bus is coupled to an n-type impurity doped region of the diode; and

forming a second electrical discharge path coupling the second plate of the MOS capacitor to the semiconductor substrate, wherein the second electrical discharge path comprises conductors without any intermediate device included in the second electrical discharge path.

2. The method of claim 1 wherein the step of forming a first electrical discharge path comprises the steps of:

forming a dielectric isolation region extending through the monocrystalline semiconductor layer to the buried insulator layer;

etching an opening through the dielectric isolation region and the buried insulation layer to expose a portion of the semiconductor substrate;

ion implanting first type conductivity determining impurities through the opening to form a PN junction diode in the semiconductor substrate; and

coupling the first voltage bus to the PN junction diode in the semiconductor substrate.

3. The method of claim 2 further comprising the steps of:

etching a second opening through a dielectric isolation region and the buried insulation layer to expose a second portion of the semiconductor substrate;

ion implanting second type conductivity determining impurities through the opening to form a contact to the semiconductor substrate; and

coupling the second voltage bus to the contact to the semiconductor substrate.

4. A method for fabricating a semiconductor on insulator (SOT) device comprising a p-type semiconductor substrate, a buried insulator layer overlying the p-type semiconductor substrate, and a monocrystalline semiconductor layer overlying the buried insulator layer, the method comprising the steps of:

forming dielectric isolation regions extending through the monocrystalline semiconductor layer;

doping a portion of the monocrystalline semiconductor layer with n-type impurity dopants to form an n-type impurity doped region that is a first plate of a capacitor;

forming an insulator layer overlying the portion of the monocrystalline semiconductor layer;

forming a conductive electrode overlying the insulator layer to form a second plate of the capacitor;

etching an opening extending through one of the dielectric isolation regions and the buried insulator layer to expose a portion of the p-type semiconductor substrate;

etching a second opening extending through one of the dielectric regions and the buried insulator layer to expose a second portion of the p-type semiconductor substrate;

doping the second portion of the p-type semiconductor substrate with p-type impurities to form a contact to the p-type semiconductor substrate;

doping a portion of the impurity doped region with n-type impurities to form first and second contact regions electrically in series with the impurity doped region, and simultaneously doping the portion of the p-type semiconductor substrate exposed through the opening with n-type impurities to form an n-type region forming a PN junction diode with the p-type semiconductor substrate;

coupling a first bus to the second plate of the capacitor and to the n-type region of the PN junction diode; and

coupling a second bus to the first plate of the capacitor and to the contact to the p-type semiconductor substrate.

5. The method of claim 4 wherein the step of forming a conductive electrode comprises the steps of:

depositing a layer of polycrystalline silicon overlying the insulator layer; and

patterning the layer of polycrystalline silicon to form a conductive electrode, a gate electrode of an NMOS transistor, and a gate electrode of a PMOS transistor.

6. The method of claim 5 wherein the step of doping the second portion of the p-type semiconductor substrate further comprises the step of forming source and drain regions of the PMOS transistor.

7. The method of claim 5 wherein the step of doping the portion of the p-type semiconductor substrate further comprises the step of forming source and drain regions of the NMOS transistor.

8. A method for fabricating a semiconductor component including a semiconductor on insulator (SOT) substrate having a first p-type semiconductor layer, a layer of insulator on the first p-type semiconductor layer, and a second semiconductor layer overlying the layer of insulator, the method comprising the steps of:

forming an n-type region in the second semiconductor layer, wherein the n-type region is a bottom capacitor plate;

forming a capacitor dielectric layer overlying the n-type region in the second semiconductor layer;

forming a top capacitor plate overlying the capacitor dielectric layer;

forming a contact area in the first p-type semiconductor layer;

implanting n-type conductivity determining ions into the second semiconductor layer to form a drain region of an MOS transistor, into the top capacitor plate, and into the n-type region to form first and second n-type contact regions adjacent to and electrically in series with the n-type region;

implanting n-type conductivity determining ions into the first semiconductor layer to form an n-type impurity doped region forming a pn junction diode with the first p-type semiconductor layer; and

depositing and patterning a metal layer to form a first voltage bus coupled to the drain region, to the top capacitor plate and to the n-type impurity doped region, and a second voltage bus coupled to the contact area in the first p-type semiconductor layer and to the n-type region in the second semiconductor layer.

9. The method of claim 8 further comprising the steps of:

depositing a first layer of insulating material overlying the second semiconductor layer;

etching the first layer of insulating material to form a first opening extending through the first layer of insulating material and exposing a portion of the drain region and a second opening exposing a portion of the n-type impurity doped region;

depositing a first layer of metal overlying the first layer of insulating material and electrically contacting the portion of the drain region and electrically contacting the portion of the impurity doped region; and

patterning the first layer of metal to form a first interconnect electrically coupled to the portion of the drain region and a second interconnect electrically coupled to the portion of the impurity doped region.

10. The method of claim 9 further comprising the steps of:

depositing a second layer of insulating material overlying the first interconnect and the second interconnect;

etching a third opening extending through the second layer of insulating material and exposing a portion of the first interconnect; and

etching a fourth opening extending through the second layer of insulating material and exposing a portion of the second interconnect.

11. The method of claim 10 wherein the step of depositing and patterning a metal layer comprises the steps of:

depositing a second layer of metal overlying the second layer of insulating material and electrically coupled to the first interconnect and to the second interconnect; and

patterning the second layer of metal to form a voltage bus coupled to the first interconnect and to the second interconnect.

12. A method for fabricating a semiconductor on insulator (SOI) device comprising a semiconductor substrate, a buried insulator layer overlying the semiconductor substrate, and a monocrystalline semiconductor layer overlying the buried insulator layer, the method comprising the steps of:

forming a MOS decoupling capacitor coupled between a first voltage bus and a second voltage bus, the MOS decoupling capacitor having;

an n-type impurity doped gate electrode material forming a first plate of the MOS decoupling capacitor and coupled to the first voltage bus;

an n-type impurity doped region in the monocrystalline semiconductor layer beneath the n-type impurity doped gate electrode material forming a second plate of the MOS decoupling capacitor and coupled to the second bus; and

first and second n-type contact regions adjacent the n-type impurity doped region; and

forming an electrical discharge path coupling the first plate of the MOS decoupling capacitor to a diode formed in the semiconductor substrate.

13. The method of claim 12 wherein the step of forming an electrical discharge path comprises the steps of:

forming a dielectric isolation region extending through the monocrystalline semiconductor layer to the buried insulator layer;

etching an opening through the dielectric isolation region and the buried insulation layer to expose a portion of the semiconductor substrate;

ion implanting first type conductivity determining impurities through the opening to form a PN junction diode in the semiconductor substrate; and

coupling the first voltage bus to the PN junction diode in the semiconductor substrate.

14. The method of claim 13 further comprising the steps of:

etching a second opening through a dielectric isolation region and the buried insulation layer to expose a second portion of the semiconductor substrate;

ion implanting second type conductivity determining impurities through the opening to form a contact to the semiconductor substrate; and

coupling the second voltage bus to the contact to the semiconductor substrate.

15. The method of claim 12 further comprising the step of forming a second electrical discharge path coupling the second plate of the MOS decoupling capacitor to the semiconductor substrate, wherein the second electrical discharge path comprises conductors without any intermediate device included in the second electrical discharge path.