Low temperature doped silicon layer formation

• US 7,718,518 B2
• Filed: 12/14/2006
• Issued: 05/18/2010
• Est. Priority Date: 12/16/2005
• Status: Active Grant

• Current Assignee: ASM International NV
• Original Assignee: ASM International NV
• Inventors: Oosterlaken, Theodorus Gerardus Maria, Fischer, Pamela René, Zagwijn, Peter Marc, Van Aerde, Steven R. A.
• Primary Examiner(s): Nguyen; Ha Tran T
• Assistant Examiner(s): Whalen; Daniel
• Application Number:
  US11/640,471
• Publication Number:
  US 20070141812A1
• Time in Patent Office: 1,251 Days
• Field of Search: 438/479, 438/488, 438/491, 438/495, 438/499, 438/501, 438/505, 438/509, 438/542, 438/564, 438/565, 438/923, 118/715, 257/E21.1, 257/E21.101, 257/E21.106
• US Class Current: 438/488
• CPC Class Codes: C23C 16/24 Deposition of silicon only
• CPC Class Codes: C23C 16/45523 Pulsed gas flow or change of composition over time
• CPC Class Codes: C23C 16/45578 Elongated nozzles, tubes with holes
• CPC Class Codes: C30B 25/02 Epitaxial-layer growth
• CPC Class Codes: C30B 29/06 Silicon
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02576 N-type
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD

Abstract

A doped silicon layer is formed in a batch process chamber at low temperatures. The silicon precursor for the silicon layer formation is a polysilane, such as trisilane, and the dopant precursor is an n-type dopant, such as phosphine. The silicon precursor can be flowed into the process chamber with the flow of the dopant precursor or separately from the flow of the dopant precursor. Surprisingly, deposition rate is independent of dopant precursor flow, while dopant incorporation linearly increases with the dopant precursor flow.

Claims

1. A method of semiconductor processing, comprising:

providing a substrate in a process chamber;

depositing a silicon layer on the substrate by exposing the substrate to temporally-separated pulses of trisilane; and

doping the silicon layer by continuously exposing the substrate to an n-type dopant precursor during and between the temporally-separated pulses of trisilane.

2. The method of claim 1, wherein depositing the silicon layer comprises maintaining reaction rate limited deposition conditions in the process chamber.

3. The method of claim 1, wherein depositing the silicon layer is performed at a temperature of less than about 500°

C.

4. The method of claim 3, wherein the deposition rate is greater than 1 Å

/min.

5. The method of claim 1, wherein the dopant precursor is a hydride.

6. The method of claim 5, wherein the dopant precursor is PH₃.

7. The method of claim 5, wherein the dopant precursor is AsH₃.

8. The method of claim 1, wherein an as-deposited surface roughness of the deposited in-situ doped silicon layer is greater than a substrate surface roughness by about 5 Å

rms or less.

9. The method of claim 8, wherein the as-deposited surface roughness is greater than the substrate surface roughness by an amount of about 3 Å

rms or less.

10. The method of claim 9, wherein the as-deposited surface roughness is greater than the substrate surface roughness by an amount of about 2 Å

rms or less.

11. The method of claim 1, wherein doping the silicon layer results in a doping level of about 4.00×

10²⁰ atoms/cm³ or more.

12. The method of claim 11, wherein the doping level is about 5.00×

10²⁰ atoms/cm³.

13. The method of claim 11, wherein a 1σ

-uniformity of the doping level is about 1% or less.

14. The method of claim 1, wherein a 1σ

-uniformity of a thickness of the layer is about 1% or less.

15. The method of claim 1, wherein depositing the silicon layer and doping the silicon layer form a doped silicon layer having a thickness of about 150 Å

or less.

16. The method of claim 15, wherein the thickness is about 100 Å

or less.

17. The method of claim 1, wherein less than 20 particles having a size of about 0.12 μ

m or greater are added per substrate.

18. The method of claim 17, wherein less than 10 particles having a size of about 0.12 μ

m or greater are added per substrate.

19. A method for forming an integrated circuit, comprising:

doping a silicon layer while depositing the silicon layer by continuously flowing a dopant precursor into a process chamber while exposing a substrate in the process chamber to temporally-separated pulses of trisilane.

20. The method of claim 19, wherein the dopant precursor is phosphine.

21. The method of claim 19, wherein the dopant precursor comprises germanium.

22. The method of claim 21, wherein the dopant precursor is germane.

23. The method of claim 19, wherein an incorporation of dopant into the silicon layer is substantially linear as a function of a partial pressure of the dopant in the process chamber.

24. The method of claim 19, wherein doping the silicon layer is performed at less than about 475°

C.

25. The method of claim 19, wherein the deposition rate is greater than about 1 Å

/min.

26. The method of claim 19, wherein depositing the silicon layer comprises forming a substantially completely continuous film before the silicon layer reaches a thickness of about 40 Å

.

27. The method of claim 19, wherein depositing the silicon layer comprises flowing trisilane into the process chamber from a vertical injector, the vertical injector comprising a plurality of vertically distributed openings.

28. The method of claim 19, wherein the process chamber is a batch process chamber.

29. The method of claim 19, wherein doping a silicon layer while depositing the silicon layer deposits the silicon layer to a thickness of about 100 Å

or less.

30. The method of claim 29, wherein doping the silicon layer results in a doping level of about 4.00×

10²⁰ atoms/cm³ or more.

31. The method of claim 30, wherein doping the silicon layer results in a doping level of about 5.00×

10²⁰ atoms/cm³.