Method for fabricating a 3-D integrated circuit using a hard mask of silicon-oxynitride on amorphous carbon

• US 7,718,546 B2
• Filed: 06/27/2007
• Issued: 05/18/2010
• Est. Priority Date: 06/27/2007
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Radigan, Steven J., Konevecki, Michael W.
• Primary Examiner(s): Toledo; Fernando L
• Assistant Examiner(s): Singal; Ankush K
• Application Number:
  US11/769,027
• Publication Number:
  US 20090004786A1
• Time in Patent Office: 1,056 Days
• Field of Search: 438/624, 438/633, 438/638, 438/758, 438/FOR.350
• US Class Current: 438/758
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1021 including diodes only
• CPC Class Codes: H01L 29/8615 Hi-lo semiconductor devices, e.g. memory devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method for fabricating a 3-D monolithic memory device. Silicon-oxynitride (Si_xO_yN_z) on amorphous carbon is used an effective, easily removable hard mask with high selectivity to silicon, oxide, and tungsten. A silicon-oxynitride layer is etched using a photoresist layer, and the resulting etched Si_xO_yN_z layer is used to etch an amorphous carbon layer. Silicon, oxide, and/or tungsten layers are etched using the amorphous carbon layer. In one implementation, conductive rails of the 3-D monolithic memory device are formed by etching an oxide layer such as silicon dioxide (SiO₂) using the patterned amorphous carbon layer as a hard mask. Memory cell diodes are formed as pillars in polysilicon between the conductive rails by etching a polysilicon layer using another patterned amorphous carbon layer as a hard mask. Additional levels of conductive rails and memory cell diodes are formed similarly to build the 3-D monolithic memory device.

Claims

1. A method for fabricating a 3-D monolithic memory device, comprising:

patterning a first silicon-oxynitride layer in a layered structure to provide a first patterned silicon-oxynitride layer, the layered structure includes a first amorphous carbon layer below the first silicon-oxynitride layer, and a first oxide layer below the first amorphous carbon layer;

patterning the first amorphous carbon layer using the first patterned silicon-oxynitride layer to provide a first patterned amorphous carbon layer;

patterning the first oxide layer using the first patterned amorphous carbon layer to provide a first patterned oxide layer;

forming a first set of conductive rails in the first patterned oxide layer, the first set of conductive rails is in a particular level of the 3-D monolithic memory device;

forming a first polycrystalline layer above the first set of conductive rails;

patterning the first polycrystalline layer to provide a first plurality of pillars which are electrically coupled from below to the first set of conductive rails, the first plurality of pillars comprise diodes in the particular level of the 3-D monolithic memory device;

forming a second oxide layer above the first plurality of pillars, a second amorphous carbon layer above the second oxide layer, and a second silicon-oxynitride layer above the second amorphous carbon layer;

patterning the second silicon-oxynitride layer to provide a second patterned silicon-oxynitride layer;

patterning the second amorphous carbon layer using the second patterned silicon-oxynitride layer to provide a second patterned amorphous carbon layer;

patterning the second oxide layer using the second patterned amorphous carbon layer to provide a second patterned oxide layer; and

forming a second set of conductive rails in the second patterned oxide layer, the first plurality of pillars are electrically coupled from above to the second set of conductive rails.

2. The method of claim 1, wherein:

the first oxide layer comprises silicon dioxide.

3. The method of claim 1, wherein:

each pillar of the first plurality of pillars has a heavily doped region of a first conductivity type, an undoped or lightly doped middle region, and a heavily doped region of a second conductivity type.

4. The method of claim 1, wherein:

the first silicon-oxynitride layer has a starting thickness of about 220 to 420 Angstroms; and

the first amorphous carbon layer has a starting thickness of approximately 2700 to 3300 Angstroms.

5. The method of claim 1, wherein:

the patterning of the first oxide layer using the first patterned amorphous carbon layer to provide the first patterned oxide layer includes patterning one or more intermediate layers using the first patterned amorphous carbon layer and patterning the first oxide layer using the one or more intermediate layers.

6. The method of claim 1, further comprising:

patterning a polycrystalline layer above the second set of conductive rails to form a second plurality of pillars which are electrically coupled from below to the second set of conductive rails.

7. The method of claim 1, further comprising:

the first patterned oxide layer is provided by forming parallel trenches in the first oxide layer.

8. The method of claim 1, further comprising:

the 3-D monolithic memory device comprises multiple levels of diodes.

9. The method of claim 1, further comprising:

the first set of conductive rails is formed in the first patterned oxide layer by filling the parallel trenches with a conductive material.

10. The method of claim 9, wherein:

the conductive material comprises at least one of tungsten and aluminum titanium nitride.