Multi-bit memory device having resistive material layers as storage node and methods of manufacturing and operating the same

• US 7,718,988 B2
• Filed: 04/06/2006
• Issued: 05/18/2010
• Est. Priority Date: 04/06/2005
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Jung-hyun
• Primary Examiner(s): Such; Matthew W
• Application Number:
  US11/278,853
• Publication Number:
  US 20060226411A1
• Time in Patent Office: 1,503 Days
• Field of Search: 257 1- 5, 257/42, 257E29088-E29089, 257E45001-E45003, 365/46, 365/148, 365/159, 365/165, 438102-104
• US Class Current: 257/2
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 11/5678 using amorphous/crystalline phase transition storage elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10N 70/063 by etching of pre-deposited switching material layers, e.g. lithography
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/801 Constructional details of multistable switching devices
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe
• CPC Class Codes: H10N 70/8833 Binary metal oxides, e.g. TaOx

Abstract

Provided are a multi-bit memory device having resistive material layers as a storage node, and methods of manufacturing and operating the same. The memory device includes a substrate, a transistor formed on the substrate, and a storage node coupled to the transistor, wherein the storage node includes: a lower electrode connected to the substrate; a first phase change layer formed on the lower electrode; a first barrier layer overlying the first phase change layer; a second phase change layer overlying the first barrier layer; and an upper electrode formed on the second phase change layer.

Claims

1. A phase change memory device including a substrate, a transistor formed on the substrate, and a storage node coupled to the transistor, wherein the storage node comprises:

a lower electrode connected to the substrate;

a first phase change layer formed on the lower electrode and having a first minimum resistance and a first maximum resistance based on the application of a first write voltage;

a first barrier layer overlying the first phase change layer and constituting an insulating layer;

a second phase change layer overlying the first barrier layer and having a second minimum resistance and a second maximum resistance based on the application of a second write voltage, which is different from the first write voltage; and

an upper electrode formed on the second phase change layer,

wherein the first barrier layer has a lower resistance than the first and second phase change layers and is thin enough to permit the tunneling of electrons.

2. The phase change memory device of claim 1, wherein the first phase change layer is formed of a chalcogenide material.

3. The phase change memory device of claim 1, wherein the second phase change layer is formed of a transition metal oxide.

4. The phase change memory device of claim 3, wherein the first barrier layer is configured to prevent the movement of oxygen from the second phase change layer formed of the transition metal oxide to the first phase change layer.

5. The phase change memory device of claim 1, further comprising a second barrier layer and a third phase change layer sequentially formed between the second phase change layer and the upper electrode.

6. The phase change memory device of claim 5, wherein the second barrier layer is a metal layer or an insulating layer having a lower resistance than the first through third phase change layers and being thin enough to allow the tunneling of electrons.

7. The phase change memory device of claim 1, wherein a resistance of the storage node substantially equals a sum of the resistance of the first phase change layer and the resistance of the second phase change layer.

8. The phase change memory device of claim 1, wherein the first minimum and maximum resistances of the first phase change layer are respectively different from the second minimum and maximum resistances of the second phase change layer.

9. The phase change memory device of claim 1, wherein the second phase change layer is formed of niobium oxide.

10. The phase change memory device of claim 9, wherein the first barrier layer is configured to prevent the movement of oxygen from the second phase change layer formed of niobium oxide to the first phase change layer.

11. The phase change memory device of claim 1, wherein the upper electrode is substantially parallel to a gate electrode of the transistor.

12. The phase change memory device of claim 1, wherein the first write voltage for causing the first phase change layer to switch between the first minimum resistance and the first maximum resistance is greater than the second write voltage for causing the second phase change layer to switch between the second minimum resistance and the second maximum resistance.

13. The phase change memory device of claim 1, wherein the first barrier layer is configured to prevent the transmission of holes between the first and second phase change layers.

14. A phase change memory device including a substrate, a transistor formed on the substrate, and a storage node coupled to the transistor, wherein the storage node comprises:

a lower electrode connected to the substrate;

a first phase change layer formed on the lower electrode and having a first minimum resistance and a first maximum resistance based on the application of a first write voltage;

a first barrier layer overlying the first phase change layer;

a second phase change layer overlying the first barrier layer and having a second minimum resistance and a second maximum resistance based on the application of a second write voltage, which is different from the first write voltage;

an upper electrode formed on the second phase change layer; and

a dielectric layer that is formed between the second phase change layer and the upper electrode and is thin enough to allow the tunneling of electrons.

15. The phase change memory device of claim 14, wherein the first phase change layer is formed of a chalcogenide material.

16. The phase change memory device of claim 14, wherein the first barrier layer is a metal layer or an insulating layer having a lower resistance than the first and second phase change layers and being thin enough to permit the tunneling of electrons.

17. The phase change memory device of claim 14, wherein the second phase change layer is formed of a transition metal oxide.

18. The phase change memory device of claim 14, further comprising a second barrier layer and a third phase change layer sequentially formed between the second phase change layer and the upper electrode.

19. The phase change memory device of claim 18, wherein the second barrier layer is a metal layer or an insulating layer having a lower resistance than the first through third phase change layers and being thin enough to allow the tunneling of electrons.

20. The phase change memory device of claim 14, wherein the first minimum and maximum resistances of the first phase change layer are respectively different from the second minimum and maximum resistances of the second phase change layer.

21. The phase change memory device of claim 14, wherein the second phase change layer is formed of niobium oxide.