Low power electrically alterable nonvolatile memory cells and arrays

• US 7,719,050 B1
• Filed: 06/10/2008
• Issued: 05/18/2010
• Est. Priority Date: 06/28/2005
• Status: Expired due to Fees

• Current Assignee: Chih-Hsin Wang
• Original Assignee: Chih-Hsin Wang
• Inventors: Wang, Chih-Hsin
• Primary Examiner(s): Nguyen; Dao H
• Application Number:
  US12/157,380
• Time in Patent Office: 707 Days
• Field of Search: 257/315, 257/316, 257/324, 257/E21.17, 257/E21.68, 365/185.18, 438/257, 438/259
• US Class Current: 257/316
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/42336 with one gate at least partly formed in a trench
• CPC Class Codes: H01L 29/47 Schottky barrier electrodes H01L29/435 takes precedence
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A memory cell comprises a body of a semiconductor material having a first conductivity type. A conductor-filter system includes a first conductor having thermal charge carriers, and a filter contacting the first conductor and including dielectrics for providing a filtering function on the charge carriers of one polarity. The filter includes a first set of electrically alterable potential barriers. A conductor-insulator system includes a second conductor and a first insulator contacting the second conductor at an interface and having a second set of electrically alterable potential barriers. A first region is spaced-apart from the second conductor. A channel of the body is defined therebetween. A second insulator is adjacent to the first region. A charge storage region is disposed in between the first and the second insulators. A word-line has a first portion and a second portion comprising the first conductor disposed over and insulated from the body.

Claims

1. A memory cell comprising:

a body of a semiconductor material having a first conductivity type;

a conductor-filter system including;

a first conductor having thermal charge carriers; and

a filter contacting the first conductor and including dielectrics for providing a filtering function on thermal charge carriers of one polarity, wherein the filter includes;

a first set of electrically alterable potential barriers for controlling flow of the thermal charge carriers of one polarity through the filter in one direction;

a conductor-insulator system including;

a second conductor having at least a portion thereof contacting the filter and having energized charge carriers from the filter; and

a first insulator contacting the second conductor at an interface and having a second set of electrically alterable potential barriers adjacent to the interface;

a first region spaced-apart from the second conductor with a channel of the body defined there between;

a second insulator adjacent to the first region;

a charge storage region disposed in between the first and the second insulators; and

a word-line of a conductor having;

a first portion disposed over and insulated from the charge storage region, and

a second portion comprising the first conductor disposed over and insulated from the body.

2. The memory cell of claim 1, wherein the filter further includes a third set of electrically alterable potential barriers for controlling flow of thermal charge carriers of an opposite polarity through the filter in another direction that is substantially opposite to the one direction.

3. The memory cell of claim 1, wherein the filter comprises:

a first dielectric disposed adjacent to the first conductor and having an energy band gap; and

a second dielectric disposed adjacent to the first dielectric, wherein the second dielectric has an energy band gap narrower than the energy band gap of the first dielectric.

4. The memory cell of claim 3, wherein the first dielectric has a first dielectric constant and the second dielectric has a dielectric constant that is substantially greater than the first dielectric constant.

5. The memory cell of claim 3, wherein the first dielectric has a first dielectric constant and a first thickness and the second dielectric has a second dielectric constant and a second thickness, and wherein a product of the second dielectric constant and the first thickness is substantially greater than a product of the first dielectric constant and the second thickness.

6. The memory cell of claim 3, wherein the first dielectric comprises oxide having a thickness in a range of about 1.5 nm to about 4 nm, and the second dielectric comprises material selected from the group consisting of nitride, oxynitride, Al₂O₃, HfO₂, TiO₂, ZrO₂, Ta₂O₅, and alloys formed thereof.

7. The memory cell of claim 3, wherein the first dielectric comprises oxynitride having a thickness in a range of about 1.5 nm to about 4 nm, and the second dielectric comprises material selected from the group consisting of nitride, Al₂O₃, HfO₂, TiO₂, ZrO₂, Ta₂O₅, and alloys formed thereof.

8. The memory cell of claim 1, wherein the charge storage region comprises conductive material having a larger work-function than a work-function of the second conductor.

9. The memory cell of claim 8, wherein the charge storage region comprises p-type polysilicon and the second conductor comprises n-type silicon.

10. The memory cell of claim 1, wherein the first region comprises a semiconductor material having a second conductivity type.

11. The memory cell of claim 1, wherein the second conductor comprises a semiconductor material having a second conductivity type.

12. The memory cell of claim 1, wherein the body comprises silicon, and the first region and the second conductor comprises a semiconductor material selected from the group including silicon, and SiGe.

13. The memory cell of claim 1, wherein the first region comprises a first connector and a first junction.

14. The memory cell of claim 13, wherein the first connector and the first junction are formed in a self-aligned manner.

15. The memory cell of claim 13, wherein the first junction comprises junction selected from the group consisting of p-n junction and Schottky junction.

16. The memory cell of claim 13, wherein the first connector comprises material selected from the group including polysilicon, poly-SiGe, SiGe, Al, Pt, Au, W, Mo, Ru, Ta, Ni, TaN, TiN, platinum-silicide, titanium silicide, tungsten-silicide, tungsten-polycide, nickel-silicide, cobalt-silicide, erbium silicide, terbium silicide, dysprosium silicide, and ytterbium silicide.

17. The memory cell of claim 1, wherein the second conductor comprises a second connector and a second junction.

18. The memory cell of claim 17, wherein the second connector and the second junction are formed in a self-aligned manner.

19. The memory cell of claim 17, wherein the second junction comprises junction selected from the group consisting of p-n junction and Schottky junction.

20. The memory cell of claim 17, wherein the second connector comprises material selected from the group including polysilicon, poly-SiGe, SiGe, Al, Pt, Au, W, Mo, Ru, Ta, Ni, TaN, TiN, platinum-silicide, titanium silicide, tungsten-silicide, tungsten-polycide, nickel-silicide, cobalt-silicide, erbium silicide, terbium silicide, dysprosium silicide, and ytterbium silicide.

21. The memory cell of claim 1, wherein the word-line comprises material selected from the group including n+ polysilicon, p+ polysilicon, poly-SiGe, Al, Pt, Au, W, Mo, Ru, Ta, Ni, TaN, TiN, and alloy formed thereof.

22. The memory cell of claim 1, further comprising a buried well of a semiconductor material having a second conductivity type and disposed in between the body and a substrate.

23. The memory cell of claim 1, wherein the energized charge carriers has an energy distribution with an energy spectrum in the range of about 30 meV to about 300 meV.

24. The memory cell of claim 1, wherein the first and the second insulators comprise dielectrics of the oxynitride system SiO_xN_1-x.

25. The memory cell of claim 1, wherein a thickness of the second insulator is thinner than a thickness of the first insulator.

26. A memory cell comprising:

a body of a semiconductor material having a first conductivity type;

a conductor-filter system including;

a first conductor having thermal charge carriers; and

a filter contacting the first conductor and including dielectrics for providing a filtering function on thermal charge carriers of one polarity, wherein the filter includes;

a first set of electrically alterable potential barriers for controlling flow of the thermal charge carriers of one polarity through the filter in one direction, and

a second set of electrically alterable potential barriers for controlling flow of thermal charge carriers of an opposite polarity through the filter in another direction that is substantially opposite to the one direction;

a conductor-insulator system including;

a second conductor having at least a portion thereof contacting the filter and having energized charge carriers from the filter; and

a first insulator contacting the second conductor at an interface and having a third set of electrically alterable potential barriers adjacent to the interface;

a first region spaced-apart from the second conductor with a channel of the body defined there between;

a second insulator adjacent to the first region;

a charge storage region disposed in between the first and the second insulators;

a word-line of a conductor having;

a first portion disposed over and insulated from the charge storage region, and

a second portion comprising the first conductor disposed over and insulated from the body; and

means for transporting the energized charge carriers over the third set of electrically alterable potential barriers onto the charge storage region.

27. The memory cell of claim 26, wherein the means is the ballistic-hole injection mechanism and wherein the energized charge carriers are ballistic light-holes.

28. The memory cell of claim 26, wherein the means is the ballistic-electron injection mechanism and wherein the energized charge carriers are ballistic electrons.

29. The memory cell of claim 26, wherein the energized charge carriers has an energy distribution with an energy spectrum in the range of about 30 meV to about 300 meV.

30. A nonvolatile memory array comprising:

a substrate;

a plurality of nonvolatile memory cells on the substrate, and arranged in a rectangular array of rows and columns, each of the plurality of nonvolatile memory cells comprising;

a body of a semiconductor material having a first conductivity type;

a conductor-filter system including;

a first conductor having thermal charge carriers; and

a filter contacting the conductor and including dielectrics for providing a filtering function on thermal charge carriers of one polarity, wherein the filter includes;

a first set of electrically alterable potential barriers for controlling flow of the thermal charge carriers of one polarity through the filter in one direction, and

a second set of electrically alterable potential barriers for controlling flow of thermal charge carriers of an opposite polarity through the filter in another direction that is substantially opposite to the one direction;

a conductor-insulator system including;

a second conductor having at least a portion thereof contacting the filter and having energized charge carriers from the filter; and

a first insulator contacting the second conductor at an interface and having a third set of electrically alterable potential barriers adjacent to the interface;

a first region spaced-apart from the second conductor with a channel of the body defined there between;

a second insulator adjacent to the first region;

a charge storage region disposed in between the first and the second insulators; and

a third conductor having;

a first portion disposed over and insulated from the charge storage region, and

a second portion comprising the first conductor disposed over and insulated from the body.

31. The nonvolatile memory array of claim 30, further comprising:

a plurality of word-lines oriented in a first direction;

a plurality of source-lines oriented in a second direction; and

a plurality of bit-lines oriented in the second direction,

wherein each of the word-lines connects the third conductor of each of the memory cells in a same row, each of the bit-lines connects the second conductor of each of the memory cells in a same column, and each of the source-lines connects the first region of each of the memory cells in a same column.

32. The nonvolatile memory array of claim 30, wherein the memory cells are formed as pairs of memory cells having each of the memory cell pairs sharing a single first region therebetween.

33. The nonvolatile memory array of claim 30, wherein the memory cells are formed as pairs of memory cells, and wherein one cell of one cell pair in one column and one cell of another cell pair in a same row and in an adjacent column shares a single first conductor therebetween.

34. The nonvolatile memory array of claim 30, wherein the substrate comprises a semiconductor material having a first conductivity type, and the nonvolatile memory array further comprising a buried well of a semiconductor material having a second conductivity type disposed in between the body of each of memory cells and the substrate.