Integrated spiral inductor

• US 7,719,083 B2
• Filed: 03/15/2005
• Issued: 05/18/2010
• Est. Priority Date: 11/12/1998
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Chang, James Y. C.
• Primary Examiner(s): Le; Thao X
• Assistant Examiner(s): Tran; Thanh Y
• Application Number:
  US11/079,717
• Publication Number:
  US 20050156700A1
• Time in Patent Office: 1,890 Days
• Field of Search: 257/528, 257531-536, 257/774, 257/E21.022, 257/E31.072, 257/277, 257/659, 257/665, 333/185, 336/200, 336/232
• US Class Current: 257/531
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01F 17/0013 with stacked layers
• CPC Class Codes: H01F 2017/0053 with means to reduce eddy currents
• CPC Class Codes: H01F 2021/125 Printed variable inductor with taps, e.g. for VCO
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H03B 5/364 the amplifier comprising field effect transistors H03B5/366 takes precedence
• CPC Class Codes: H03D 7/161 all the frequency changers being connected in cascade
• CPC Class Codes: H03D 7/18 Modifications of frequency-changers for eliminating image frequencies H03D7/16 takes precedence
• CPC Class Codes: H03G 1/0029 using FETs
• CPC Class Codes: H03H 11/1291 Current or voltage controlled filters
• CPC Class Codes: H03J 1/0075 where the receiving frequencies of the stations are stored in a permanent memory, e.g. ROM
• CPC Class Codes: H03J 2200/10 Tuning of a resonator by means of digitally controlled capacitor bank
• CPC Class Codes: H03J 3/04 Arrangements for compensating for variations of physical values, e.g. temperature
• CPC Class Codes: H03J 3/08 by varying a second parameter simultaneously with the tuning, e.g. coupling bandpass filter
• CPC Class Codes: H03J 3/185 with varactors, i.e. voltage variable reactive diodes
• CPC Class Codes: H03L 7/103 : the additional signal being a digital signal
• CPC Class Codes: H03L 7/23 : with pulse counters or frequency dividers

Abstract

An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors with shields to increase circuit Q. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver. ESD protection is provided by a pad ring and ESD clamping structure that maintains signal integrity. Also provided are shunts at each pin to discharge ESD build up. The shunts utilize a gate boosting structure to provide sufficient small signal RF performance, and minimal parasitic loading.

Claims

1. An integrated circuit inductor, comprising:

a substrate;

a plurality of distinct n+ diffusion regions formed in the substrate;

a conductive strip of metal physically contacting and thereby connecting an individual n+ diffusion region to an adjacent n+ diffusion region; and

an inductor metallization pattern in contact with the substrate and directly above the n+ diffusion regions.

2. The integrated circuit inductor of claim 1, wherein there is a gap between two n+ regions and polysilicon is filled in the gap.

3. The integrated circuit inductor of claim 2, wherein the plurality of distinct n+ diffusion regions and the polysilicon are not electrically coupled to each other.

4. The integrated circuit inductor of claim 1, wherein the inductor metallization pattern includes a plurality of tracks having a common input and a common output.

5. The integrated circuit inductor of claim 4, wherein tracks of the plurality of tracks are arranged so as to be parallel to one another from the common input to the common output.

6. The integrated circuit inductor of claim 4, wherein a single layer of the inductor metallization pattern includes the plurality of tracks.

7. The integrated circuit inductor of claim 4, wherein the plurality of tracks is included among a plurality of layers of the inductor metallization pattern.

8. The integrated circuit inductor of claim 7, wherein a first track at a first layer of the inductor metallization pattern and a second track at a second layer of the inductor metallization pattern are connected in parallel by a first via at the common input and by a second via at the common output.

9. The integrated circuit inductor of claim 1, further comprising a conductive metal element electrically coupled to the plurality of distinct n+ diffusion regions.

10. The integrated circuit inductor of claim 9, wherein the n+ diffusion regions are configured in rows, and wherein the conductive metal element connects n+ diffusion regions of a row together.

11. The integrated circuit inductor of claim 10, wherein the conductive metal element connects n+ diffusion regions of a plurality of rows together.

12. The integrated circuit inductor of claim 11, wherein the conductive metal element connects the n+ diffusion regions of the plurality of rows to a ground potential.

13. The integrated circuit inductor of claim 9, wherein the conductive metal element is ring-shaped.

14. The integrated circuit inductor of claim 13, wherein the conductive metal element includes a cut to suppress a ground loop current.

15. The integrated circuit inductor of claim 14, wherein the cut acts as a barrier to current flow.

16. The integrated circuit inductor of claim 1, wherein the inductor metallization pattern is a spiral inductor metallization pattern.

17. The integrated circuit inductor of claim 1, wherein the spiral inductor metallization pattern is substantially square.

18. The integrated circuit inductor of claim 1, wherein the spiral inductor metallization pattern is substantially octagonal.

19. The integrated circuit inductor of claim 1, wherein the spiral inductor metallization pattern is substantially circular.

20. The integrated circuit inductor of claim 1, wherein the inductor metallization pattern is a symmetric inductor metallization pattern.

21. The integrated circuit inductor of claim 1, wherein the plurality of distinct n+ diffusion regions are constructed and arranged to form a fingered pattern of distinct n+ diffusion regions.