Semiconductor device

• US 7,719,102 B2
• Filed: 06/04/2008
• Issued: 05/18/2010
• Est. Priority Date: 06/18/2002
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Shinogi, Hiroyuki, Takao, Yukihiro, Noma, Takashi
• Primary Examiner(s): EVERHART, CARIDAD
• Application Number:
  US12/133,171
• Publication Number:
  US 20080265424A1
• Time in Patent Office: 713 Days
• Field of Search: 257/674, 257/684, 257/697, 257/E23.174, 257/E23.011, 257/E23.067, 257/E21.579, 257/E23.008, 257/E23.015, 257/E23.157, 257/E23.169
• US Class Current: 257/697
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2224/02 Bonding areas; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02371 connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13024 the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides

Abstract

A manufacturing method of a semiconductor device of this invention includes forming metal pads on a Si substrate through a first oxide film, bonding the Si substrate and a holding substrate which bolsters the Si substrate through a bonding film, forming an opening by etching the Si substrate followed by forming a second oxide film on a back surface of the Si substrate and in the opening, forming a wiring connected to the metal pads after etching the second oxide film, forming a conductive terminal on the wiring, dicing from the back surface of the Si substrate to the bonding film and separating the Si substrate and the holding substrate.

Claims

1. A semiconductor device comprising:

a semiconductor substrate;

a metal pad disposed on a top surface of the semiconductor substrate;

an electrode connection portion disposed on the top surface of the semiconductor substrate and electrically connected to the metal pad, the electrode connection portion being configured to be connected to an external electric connection portion;

a first insulation film disposed on a side surface and a bottom surface of the semiconductor substrate; and

a metal wiring in contact with the metal pad and extending along the side surface and the bottom surface of the semiconductor substrate,

wherein the electrode connection portion is separated from the metal pad in a direction parallel to the top surface of the semiconductor substrate.

2. The semiconductor device of claim 1, further comprising a protection film covering the metal wiring.

3. The semiconductor device of claim 1, wherein a top surface of the electrode connection portion is exposed for external connection to the external electric connection portion.

4. The semiconductor device of claim 1, wherein the first insulation film comprises a single layer that is homogenous in terms of composition thereof.

5. The semiconductor device of claim 1, wherein the metal pad extends beyond a lateral edge of the semiconductor substrate in a direction parallel to the top surface of the semiconductor substrate.

6. The semiconductor device of claim 1, further comprising a first wiring disposed on the top surface of the semiconductor substrate and electrically connecting the electrode connection portion and the metal pad.

7. The semiconductor device of claim 6, further comprising a second insulation film disposed on the first wiring and having an opening above the electrode connection portion.

8. The semiconductor device of claim 7, wherein the second insulation film comprises a polyimide resin or an epoxy resin.

9. The semiconductor device of claim 1, further comprising a conductive terminal electrically connected to the metal wiring.

10. The semiconductor device of claim 9, further comprising a cushioning material disposed between the metal wiring and the semiconductor substrate under the conductive terminal.

11. A semiconductor device comprising:

a semiconductor substrate;

a metal pad disposed on a top surface of the semiconductor substrate;

an electrode connection portion disposed on the top surface of the semiconductor substrate and electrically connected to the metal pad, the electrode connection portion being configured to be connected to an external electric connection portion;

a first insulation film disposed on a side surface and a bottom surface of the semiconductor substrate; and

a metal wiring in contact with the metal pad and extending along the side surface and the bottom surface of the semiconductor substrate,

wherein the electrode connection portion comprises a stack of a nickel layer, a gold layer and a copper layer or a stack of a nickel layer, a gold layer, a copper layer and a gold layer.

12. A semiconductor device comprising:

a first semiconductor device comprising a semiconductor substrate, a metal pad disposed on a top surface of the semiconductor substrate, an electrode connection portion disposed on the top surface of the semiconductor substrate and electrically connected to the metal pad, an insulation film disposed on a side surface and a bottom surface of the semiconductor substrate and a metal wiring in contact with the metal pad and extending along the side surface and the bottom surface of the semiconductor substrate, the electrode connection portion being separated from the metal pad in a direction parallel to the top surface of the semiconductor substrate; and

a second semiconductor device stacked on the first semiconductor device and comprising an electric connection portion that is in contact with the electrode connection portion of the first semiconductor device.

13. A semiconductor device comprising:

a first semiconductor device comprising a first semiconductor substrate, a first metal pad disposed on a top surface of the first semiconductor substrate, a first electrode connection portion disposed on the top surface of the first semiconductor substrate and electrically connected to the first metal pad, a first insulation film disposed on a side surface and a bottom surface of the first semiconductor substrate, a first metal wiring in contact with the first metal pad and extending along the side surface and the bottom surface of the first semiconductor substrate and a first conductive terminal disposed on the bottom surface of the first semiconductor substrate and electrically connected to the first metal wiring, the first electrode connection portion being separated from the first metal pad in a direction parallel to the top surface of the first semiconductor substrate; and

a second semiconductor device comprising a second semiconductor substrate, a second metal pad disposed on a top surface of the second semiconductor substrate, a second electrode connection portion disposed on the top surface of the second semiconductor substrate and electrically connected to the second metal pad, a second insulation film disposed on a side surface and a bottom surface of the second semiconductor substrate, a second metal wiring in contact with the second metal pad and extending along the side surface and the bottom surface of the second semiconductor substrate and a second conductive terminal disposed on the bottom surface of the second semiconductor substrate and electrically connected to the second metal wiring,

wherein the first and second semiconductor devices are stacked together so that the first electrode connection portion of the first semiconductor device is in contact with the second conductive terminal of the second semiconductor device.

14. A semiconductor device comprising:

a semiconductor substrate having a via hole penetrating through the semiconductor substrate;

a metal pad disposed on a top surface of the semiconductor substrate so as to cover the via hole;

an electrode connection portion disposed on the top surface of the semiconductor substrate and electrically connected to the metal pad, the electrode connection portion being configured to be connected to an external electric connection portion;

a first insulation film disposed on a sidewall of the via hole; and

a metal film disposed on the first insulation film in the via hole so as to be in contact with the metal pad.

15. The semiconductor device of claim 14, wherein the electrode connection portion comprises a stack of a nickel layer, a gold layer and a copper layer or a stack of a nickel layer, a gold layer, a copper layer and a gold layer.

16. The semiconductor device of claim 14, wherein the electrode connection portion is disposed on the metal pad.

17. The semiconductor device of claim 14, further comprising an interconnection disposed on the top surface of the semiconductor substrate and electrically connecting the electrode connection portion and the metal pad.

18. The semiconductor device of claim 14, further comprising a conductive terminal disposed on a bottom surface of the semiconductor substrate and electrically connected to the metal film.

19. The semiconductor device of claim 18, further comprising a wiring disposed on the bottom surface of the semiconductor substrate and in contact with the metal film, wherein the conductive terminal is on the wiring.

20. The semiconductor device of claim 14, further comprising a second insulation film disposed on the top surface of the semiconductor substrate and having an opening to expose the electrode connection portion.

21. The semiconductor device of claim 20, wherein the second insulation film comprises a polyimide resin or an epoxy resin.

22. A semiconductor device comprising:

a first semiconductor device comprising a semiconductor substrate having a via hole penetrating through the semiconductor substrate, a metal pad disposed on a top surface of the semiconductor substrate so as to cover the via hole, an electrode connection portion disposed on the top surface of the semiconductor substrate and electrically connected to the metal pad, an insulation film disposed on a sidewall of the via hole and a metal film disposed on the insulation film in the via hole so as to be in contact with the metal pad;

a second semiconductor device stacked on the first semiconductor device and comprising an electric connection portion that is in contact with the electrode connection portion of the first semiconductor device.

23. A stacked layer type semiconductor device, comprising:

a first semiconductor device comprising a first semiconductor substrate having a first via hole penetrating through the first semiconductor substrate, a first metal pad disposed on a top surface of the first semiconductor substrate so as to cover the first via hole, a first electrode connection portion disposed on the top surface of first the semiconductor substrate and electrically connected to the first metal pad, a first insulation film disposed on a sidewall of the first via hole and a first metal film disposed on the first insulation film in the via hole so as to be in contact with the first metal pad and a first conductive terminal disposed on a bottom surface of the first semiconductor substrate and electrically connected to the first metal film; and

a second semiconductor device comprising a second semiconductor substrate having a second via hole penetrating through the second semiconductor substrate, a second metal pad disposed on a top surface of the second semiconductor substrate so as to cover the second via hole, a second electrode connection portion disposed on the top surface of second the semiconductor substrate and electrically connected to the second metal pad, a second insulation film disposed on a sidewall of the second via hole and a second metal film disposed on the second insulation film in the via hole so as to be in contact with the second metal pad and a second conductive terminal disposed on a bottom surface of the second semiconductor substrate and electrically connected to the second metal film,

wherein the first and second semiconductor devices are stacked together so that the first electrode connection portion of the first semiconductor device is in contact with the second conductive terminal of the second semiconductor device.