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Active-load dominant circuit for common-mode glitch interference cancellation

  • US 7,719,325 B1
  • Filed: 11/18/2008
  • Issued: 05/18/2010
  • Est. Priority Date: 11/18/2008
  • Status: Active Grant
First Claim
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1. An active-load dominant circuit for common-mode glitch interference cancellation, biased between a first voltage potential and a second voltage potential, comprising:

  • a pair of pull-up networks for providing access to said first voltage potential in response to a clock signal or a complemented clock signal; and

    a pair of active-load networks placed between said pair of pull-up networks and said second voltage potential, for generating at least one set signal and at least one reset signal for a latch, wherein said pair of active-load networks comprise at least one active device at each active-load network for accessing said second voltage potential in response to said clock signal or said complemented clock signal; and

    said pair of pull-up networks comprise a first resistor and a first PMOS transistor in one pull-up network, said first resistor being connected in series with said first PMOS transistor, and comprise a second resistor and a second PMOS transistor in the other pull-up network, said second resistor being connected in series with said second PMOS transistor.

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