Active-load dominant circuit for common-mode glitch interference cancellation

• US 7,719,325 B1
• Filed: 11/18/2008
• Issued: 05/18/2010
• Est. Priority Date: 11/18/2008
• Status: Active Grant

• Current Assignee: WUXI Wenxin Electronics Technology Company Limited
• Original Assignee: Grenergy Opto, Inc.
• Inventors: Chen, Pei-Yuan, Wang, Yen-Ping, Wang, Yen-Hui
• Primary Examiner(s): Donovan; Lincoln
• Assistant Examiner(s): Hernandez; William
• Application Number:
  US12/273,011
• Publication Number:
  US 20100123501A1
• Time in Patent Office: 546 Days
• Field of Search: 326/82, 326/83, 326/87, 326/88, 327/34, 327/108, 327/109, 327/111, 327/112, 327/311, 327/382, 327/551, 327/552
• US Class Current: 327/112
• CPC Class Codes: H03K 17/162 without feedback from the output circuit to the control circuit
• CPC Class Codes: H03K 5/1252 Suppression or limitation of noise or interference specially adapted for transmission systems H04B15/00, H04L25/08

Abstract

An active-load dominant circuit for common-mode glitch interference cancellation, biased between a first voltage potential and a second voltage potential with an accompanying common-mode glitch interferer. The active-load dominant circuit includes a pair of pull-up networks and a pair of active-load networks. The common-mode glitch interferer is cancelled out due to a symmetric structure of the pair of pull-up networks. At least one set signal and at least one reset signal are provided to a latch in response to a clock signal or a complemented clock signal. At least one of the set signal and the reset signal can be pulled up to the first voltage potential or pulled down to the second voltage potential. The voltage difference of the set signal and the reset signal is large enough for a latch.

Claims

1. An active-load dominant circuit for common-mode glitch interference cancellation, biased between a first voltage potential and a second voltage potential, comprising:

a pair of pull-up networks for providing access to said first voltage potential in response to a clock signal or a complemented clock signal; and

a pair of active-load networks placed between said pair of pull-up networks and said second voltage potential, for generating at least one set signal and at least one reset signal for a latch, wherein said pair of active-load networks comprise at least one active device at each active-load network for accessing said second voltage potential in response to said clock signal or said complemented clock signal; and

said pair of pull-up networks comprise a first resistor and a first PMOS transistor in one pull-up network, said first resistor being connected in series with said first PMOS transistor, and comprise a second resistor and a second PMOS transistor in the other pull-up network, said second resistor being connected in series with said second PMOS transistor.

2. The active-load dominant circuit for common-mode glitch interference cancellation as recited in claim 1, wherein said pair of active-load networks comprise a third resistor connected in series with a first NMOS transistor in one active-load network, and provide said latch with a set signal from one end of said third resistor, and a reset signal from one end of a fourth resistor, wherein said fourth resistor connected in series with a second NMOS transistor in the other active-load network.

3. The active-load dominant circuit for common-mode glitch interference cancellation as recited in claim 1, wherein said pair of active-load networks comprise a third resistor connected in series with a first NMOS transistor in one active-load network, and comprise a fourth resistor connected in series with a second NMOS transistor in the other active-load network.

4. The active-load dominant circuit for common-mode glitch interference cancellation as recited in claim 2, wherein said pair of active-load networks provide said latch with a set signal from the drain of said first NMOS transistor and a reset signal from the drain of said second NMOS transistor.

5. The active-load dominant circuit for common-mode glitch interference cancellation as recited in claim 2, further comprises another set signal from the other end of said third resistor and another reset signal from the other end of said fourth resistor.

6. The active-load dominant circuit for common-mode glitch interference cancellation as recited in claim 3, wherein said pair of active-load networks provide said latch with a set signal from the drain of said first NMOS transistor and a reset signal from the drain of said second NMOS transistor.

7. The active-load dominant circuit for common-mode glitch interference cancellation as recited in claim 1, wherein said pair of active-load networks comprise a third resistor connected in series with a first NMOS transistor in said one pull-up network, and provide said latch with a set signal from one end of said third resistor, and a reset signal from one end of a fourth resistor, wherein said fourth resistor is connected in series with a second NMOS transistor in the other active-load network, and wherein said complemented clock signal is coupled to the gate of said first PMOS transistor, the gate of said second PMOS transistor, the gate of said first NMOS transistor, and the drain of said third PMOS transistor, and wherein said clock signal is coupled to the gate of said third PMOS transistor, the gate of said fourth PMOS transistor, the gate of said second NMOS transistor, and the drain of said first PMOS transistor.

8. The active-load dominant circuit for common-mode glitch interference cancellation as recited in claim 1, wherein said pair of active-load networks comprise a first NMOS transistor in said one pull-up network, and comprise a second NMOS transistor in the other active-load network, and wherein said complemented clock signal is coupled to the gate of said first PMOS transistor, the gate of said second PMOS transistor, the gate of said first NMOS transistor, and the drain of said third PMOS transistor, and wherein said clock signal is coupled to the gate of said third PMOS transistor, the gate of said fourth PMOS transistor, the gate of said second NMOS transistor, and the drain of said first PMOS transistor.

9. The active-load dominant circuit for common-mode glitch interference cancellation as recited in claim 1, wherein said pair of active-load networks comprise a third resistor connected in series with a first NMOS transistor in said one pull-up network, and provide said latch with a set signal from one end of said third resistor, and a reset signal from one end of a fourth resistor, wherein said fourth resistor is connected in series with a second NMOS transistor in the other active-load network, and wherein said complemented clock signal is coupled to the gate of said first PMOS transistor, the source of said second PMOS transistor, and the gate of said first NMOS transistor, and wherein said clock signal is coupled to the gate of said second PMOS transistor, the gate of said second NMOS transistor, and the source of said first PMOS transistor.

10. The active-load dominant circuit for common-mode glitch interference cancellation as recited in claim 1, wherein said pair of active-load networks comprise a third resistor connected in series with a first NMOS transistor in one active-load network, and comprise a fourth resistor connected in series with a second NMOS transistor in the other active-load network, and wherein said complemented clock signal is coupled to the gate of said first PMOS transistor, the gate of said first NMOS transistor, and the source of said second PMOS transistor, and wherein said clock signal is coupled to the gate of said second PMOS transistor, the gate of said second NMOS transistor, and the source of said first PMOS transistor.

11. An active-load dominant circuit for common-mode glitch interference cancellation, biased between a first voltage potential and a second voltage potential, comprising:

a pair of pull-up networks for providing access said first voltage potential in response to a clock signal or a complemented clock signal; and

a pair of active-load networks placed between said pair of pull-up networks and said second voltage potential, for generating at least one set signal and at least one reset signal for a latch, wherein said pair of active-load networks comprise at least one active device at each active-load network for accessing to said second voltage potential in response to said clock signal or said complemented clock signal; and

said pair of pull-up networks comprise a first resistor, a first PMOS transistor and a second PMOS transistor in one pull-up network, said first resistor being connected in parallel with said first PMOS transistor and in series with said second PMOS transistor, and comprise a second resistor, a third PMOS transistor and a fourth PMOS transistor in the other pull-up network, said second resistor being connected in parallel with said third PMOS transistor and in series with said fourth PMOS transistor.