Multiprocessor system, processor and interrupt control method

• US 7,721,035 B2
• Filed: 08/22/2007
• Issued: 05/18/2010
• Est. Priority Date: 09/08/2006
• Status: Expired due to Fees

• Current Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Original Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Inventors: Utsumi, Keiko
• Primary Examiner(s): Myers; Paul R
• Application Number:
  US11/843,503
• Publication Number:
  US 20080065803A1
• Time in Patent Office: 1,000 Days
• Field of Search: 710260-269
• US Class Current: 710/268
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence

Abstract

A first processor in a multiprocessor system for processing interrupts by a plurality of processors accepts an interrupt and executes first interrupt processing in accordance with the accepted interrupt. In the first interrupt processing, second interrupt processing corresponding to the accepted interrupt is assigned to a second processor.

Claims

1. A multiprocessor system for processing interrupts by a plurality of processors, wherein said multiprocessor system comprises:

a first processor,

wherein said first processor comprises;

an accepting unit configured to accept a first interrupt;

a management unit configured to manage a state of a second interrupt processing corresponding to the first interrupt and a state of a second processor; and

an executing unit configured to execute a first interrupt processing in accordance with the first interrupt accepted by the accepting unit,

wherein, in the first interrupt processing, the executing unit assigns, to the second processor, the second interrupt processing corresponding to the first interrupt accepted by the accepting unit when the second interrupt processing is in a processable state and the second processor is in a state of idle,

wherein the executing unit sets the second interrupt processing to a standby state and sets the first interrupt processing to a first standby state when the second interrupt processing is in the processable state and the second processor is in a state of in use, and

wherein the executing unit sets the first interrupt processing to a second standby state when the second interrupt processing is in progress based on a second interrupt or the second interrupt processing is in the standby state based on the second interrupt.

2. The system according to claim 1, wherein the executing unit selects the second processor in the first interrupt processing.

3. The system according to claim 1, wherein the executing unit assigns the second interrupt processing corresponding to the first interrupt to the second processor in accordance with the cause of the first interrupt accepted by the accepting unit.

4. The system according to claim 1, wherein the executing unit assigns the second interrupt processing to the second processor in such a manner that it is not executed in parallel with corresponding interrupt processing.

5. The system according to claim 1, wherein the first interrupt set to the second standby state is set to the second standby state until the second interrupt processing becomes the processable state.

6. The system according to claim 1, wherein the executing unit assigns the second interrupt processing corresponding to an interrupt of a specific cause to a specific processor.

7. The system according to claim 1, wherein the executing unit transmits software, which is for executing the second interrupt processing, to the second processor.

8. The system according to claim 1, wherein the first processor executes the first interrupt processing by software.

9. The system according to claim 1, further comprising an external interrupt controller and an internal interrupt controller,

wherein the external interrupt controller notifies said internal interrupt controller of an external interrupt, and the internal interrupt controller notifies the first processor of an external interrupt.

10. A processor used in a multiprocessor system for processing interrupts by a plurality of processors, the processor comprising:

an accepting unit configured to accept a first interrupt;

an executing unit configured to execute a first interrupt processing in accordance with the first interrupt accepted by the accepting unit; and

a management unit configured to manage a state of a second interrupt processing corresponding to the first interrupt and a state of a second processor,

wherein, in the first interrupt processing, the executing unit assigns, to the second processor, the second interrupt processing corresponding to the first interrupt accepted by the accepting unit when the second interrupt processing is in a processable state and the second processor is in a state of idle,

wherein the executing unit sets the second interrupt processing to a standby state and sets the first interrupt processing to a first standby state when the second interrupt processing is in the processable state and the second processor is in a state of in use, and

wherein the executing unit sets the first interrupt processing to a second standby state when the second interrupt processing is in progress based on a second interrupt or the second interrupt processing is in the standby state based on the second interrupt.

11. The processor according to claim 10, wherein the executing unit assigns the corresponding second interrupt processing to the second processor in accordance with an interrupt cause accepted by the accepting unit.

12. The processor according to claim 10, wherein the executing unit assigns the second interrupt processing to the second processor in such a manner that it is not executed in parallel with corresponding interrupt processing.

13. The processor according to claim 10, wherein the first interrupt set to the second standby state is set to the second standby state until the second interrupt processing becomes the processable state.

14. An interrupt control method in a multiprocessor system for processing interrupts by a plurality of processors, the method comprising:

accepting a first interrupt and executing a first interrupt processing by a first processor in accordance with the accepted first interrupt;

managing a state of a second interrupt processing corresponding to the first interrupt and a state of a second processor;

assigning, to the second processor, the second interrupt processing corresponding to the accepted first interrupt when the second interrupt processing is in a processable state and the second processor is in a state of idle;

setting the second interrupt processing to a standby state and the first interrupt processing to a first standby state when the second interrupt processing is in the processable state and the second processor is in a state of in use; and

setting the first interrupt processing to a second standby state when the second interrupt processing is in progress based on a second interrupt or the second interrupt processing is in the standby state based on the second interrupt.

15. The method according to claim 14, wherein in the first interrupt processing, corresponding second interrupt processing is assigned to the second processor in accordance with a cause of the accepted first interrupt.

16. The method according to claim 14, wherein in the first interrupt processing, the second interrupt processing is assigned to the second processor in such a manner that it is not executed in parallel with corresponding interrupt processing.

17. The method according to claim 14, wherein an external interrupt controller notifies an internal interrupt controller of an external interrupt;

and

the internal interrupt controller notifies the first processor of an external interrupt.

18. The method according to claim 14, wherein the first interrupt set to the second standby state is set to the second standby state until the second interrupt processing becomes the processable state.

19. A computer-readable storage medium storing a computer program, said computer program comprising code for:

accepting a first interrupt;

executing a first interrupt processing in accordance with the accepted first interrupt;

managing a state of a second interrupt processing corresponding to the first interrupt and a state of a second processor;

assigning, to the second processor, the second interrupt processing corresponding to the accepted first interrupt when the second interrupt processing is in a processable state and the second processor is in a state of idle;

setting the second interrupt processing to a standby state and the first interrupt processing to a first standby state when the second interrupt processing is in the processable state and the second processor is in a state of in use; and

setting the first interrupt processing to a second standby state when the second interrupt processing is in progress based on a second interrupt or the second interrupt processing is in the standby state based on the second interrupt.

20. The storage medium according to claim 19, wherein in the first interrupt processing, corresponding second interrupt processing is assigned to the second processor in accordance with a cause of the accepted first interrupt.

21. The storage medium according to claim 19, wherein in the first interrupt processing, the second interrupt processing is assigned to the second processor in such a manner that it is not executed in parallel with corresponding interrupt processing.

22. The storage medium according to claim 19, wherein the first interrupt set to the second standby state is set to the second standby state until the second interrupt processing becomes the processable state.