System and method for providing flexible signal routing and timing

• US 7,721,036 B2
• Filed: 05/31/2005
• Issued: 05/18/2010
• Est. Priority Date: 06/01/2004
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Quickturn Design Systems Incorporated (Cadence Group)
• Inventors: Maher, John A., Poplack, Mitchell G.
• Primary Examiner(s): Rinehart; Mark
• Assistant Examiner(s): Zaman; Faisal M
• Application Number:
  US11/140,714
• Publication Number:
  US 20050267727A1
• Time in Patent Office: 1,813 Days
• Field of Search: 710/305, 710/306, 710/31, 703/25
• US Class Current: 710/305
• CPC Class Codes: H04L 43/50 Testing arrangements

Abstract

A target interface system for flexibly routing and timing communication signals exchanged between selected components of a communication system and methods for manufacturing and using same. Under the control of a host system, the target interface system samples an output data signal provided by the host system and includes a reconfigurable datapath for flexibly routing the sampled data signal to a selected target I/O pin of the target interface system. The selected target I/O pin provides the sampled data signal as an outgoing target data signal to a target system and likewise receives an incoming target data signal from the target system. Upon sampling the incoming target data signal, the target interface system flexibly routes the sampled data signal to the host system as an input data signal. The target interface system thereby facilitates exchanges of communication signals between the host system and the target system.

Claims

1. A target interface logic for facilitating exchanges of communication signals between a hardware logic emulation system and a target system, the hardware logic emulation system having a plurality of programmable logic devices or processor chips, the target system verifying a logic design being emulated by the hardware logic emulation system, the target interface logic comprising:

at least one control signal connection that receives a system clock signal and a synchronization signal from the hardware logic emulation system, said synchronization signal initiating an emulation cycle that comprises a predetermined number of system clock cycles of said system clock signal;

a plurality of output data connections that receives output data signals from the hardware logic emulation system, said output data signals being dynamic during said emulation cycle;

a plurality of input data connections that provides input data signals to the hardware logic emulation system, said input data signals being dynamic during said emulation cycle;

a plurality of reconfigurable bidirectional connections that exchanges target data signals with the target system, said target data signals being dynamic during said emulation cycle;

a plurality of field programmable gate arrays; and

a configuration memory space storing configuration information,

wherein at least one of the plurality of field programmable gate arrays is configured according to the configuration information to couple a first reconfigurable portion of the plurality of input data connections and a first reconfigurable portion of the plurality of reconfigurable bidirectional connections, and to couple a first reconfigurable portion of the plurality of output data connections and the first reconfigurable portion of the plurality of reconfigurable bidirectional connections,

wherein the target interface logic reconfigurably schedules exchange of the target data signals between the hardware emulation logic and the target system according to the configuration information, and

wherein at least one reconfigurable bidirectional connection of said reconfigurable bidirectional connections is configurable to change its configuration between providing outgoing target data signals and receiving incoming target data signals during said emulation cycle.

2. The target interface logic of claim 1, wherein said target interface logic stores at least one stored data value and wherein, during said first system clock cycle of said system clock cycles of said emulation cycle, said target interface logic processes said sampled output data signals and said at least one stored data value to provide said outgoing target data signals.

3. The target interface logic of claim 2, wherein said at least one stored data value includes a data value selected from a group consisting of a preselected fixed logic level and an output data signal sampled during a previous system clock cycle.

4. The target interface logic of claim 1, wherein said target interface logic stores at least one stored data value and wherein, during said first system clock cycle of said system clock cycles of said emulation cycle, said target interface logic processes said sampled target data signals and said at least one stored data value to provide said input data signals.

5. The target interface logic of claim 4, wherein said at least one stored data value includes a data value selected from a group consisting of a preselected fixed logic level and an output data signal sampled during a previous system clock cycle.

6. The target interface logic of claim 1,

wherein, during a first system clock cycle of said emulation cycle, said target interface logic samples a first output data signal from a selected output data connection of the plurality of output data connections,

wherein, during a second system clock cycle of said emulation cycle, said target interface logic samples a second output data signal from said selected output data connection of the plurality of output data connections, and

wherein, during a third system clock cycle of said emulation cycle, said target interface logic provides said first and second output data signals to the target system via first and second reconfigurable bidirectional connections of the plurality of reconfigurable bidirectional connections respectively.

7. The target interface logic of claim 6, wherein said first and second system clock cycles comprise different clock cycles of said emulation cycle.

8. The target interface logic of claim 7, wherein said second system clock cycle is disposed between said first and third system clock cycles.

9. The target interface logic of claim 6, wherein said second and third system clock cycles comprise the same system clock cycle.

10. The target interface logic of claim 6, wherein said target interface logic stores said first output data signal.

11. The target interface logic of claim 1,

wherein, during a first system clock cycle of said emulation cycle, said target interface logic samples first and second output data signals from first and second output data connections of the plurality of output data connections, respectively,

wherein, during a second system clock cycle of said emulation cycle, said target interface logic provides said first output data signal to the target system via a selected reconfigurable bidirectional connection of the plurality of reconfigurable bidirectional connections, and

wherein, during a third system clock cycle of said emulation cycle, said target interface logic provides said second output data signal to the target system via said selected reconfigurable bidirectional connection of the plurality of reconfigurable bidirectional connections.

12. The target interface logic of claim 11, wherein said second and third system clock cycles comprise different clock cycles of said emulation cycle.

13. The target interface logic of claim 12, wherein said second system clock cycle is disposed between said first and third system clock cycles.

14. The target interface logic of claim 11, wherein said second and third system clock cycles comprise the same system clock cycle.

15. The target interface logic of claim 11, wherein said target interface logic stores said second output data signal.

16. The target interface logic of claim 1, wherein said configuration memory space includes a memory subspace that stores said configuration information and status information for at least one of said output data connections and said reconfigurable bidirectional connections on a time-independent basis.

17. The target interface logic of claim 1, wherein said configuration memory space includes a memory subspace that stores said configuration information and status information for at least one of said output data connections and said reconfigurable bidirectional connections on a time-dependent basis.

18. The target interface logic of claim 1, wherein one of said bidirectional reconfigurable connections provides outgoing target data signals to the target system during said first system clock cycle of said system clock cycles of said emulation cycle and receives incoming target data signals from the target system during said second system clock cycle of said system clock cycles of said emulation cycle.

19. A communication system for exchanging communication signals, comprising:

a first system that provides a system clock signal, a synchronization signal, and output data signals and that receives input data signals, the first system having a plurality of programmable logic devices or processor chips, said synchronization signal initiating a system cycle that comprises a predetermined number of system clock cycles of said system clock signal; and

an interface logic that facilitates said exchanges of said communication signals with a second system verifying a logic design being emulated by the first system, and including;

at least one control signal connection that receives said system clock signal and said synchronization signal;

a plurality of output data connections that receives said output data signals, said output data signals being dynamic during said system cycle;

a plurality of input data connections that provides said input data signals, said input data signals being dynamic during said system cycle;

a plurality of reconfigurable bidirectional connections that exchanges bidirectional data signals with the second system, said bidirectional data signals being dynamic during said system cycle;

a plurality of field programmable gate arrays; and

a configuration memory space storing configuration information,

wherein at least one of the plurality of field programmable gate arrays is configured according to the configuration information to couple a first reconfigurable of the plurality of input data connections and a first reconfigurable portion of the plurality of reconfigurable bidirectional connections, and to couple a first reconfigurable portion of the plurality of output data connections and the first reconfigurable portion of the plurality of reconfigurable bidirectional connections,

wherein the target interface logic reconfigurably schedules exchange of the target data signals between the hardware emulation logic and the target system according to the configuration information, and

wherein at least one reconfigurable bidirectional connection of said reconfigurable bidirectional connections is configurable to change its configuration between providing outgoing target data signals and receiving incoming target data signals during said system cycle.

20. The communication system of claim 19, wherein said first system comprises a hardware logic emulation system.

21. The communication system of claim 20, wherein said second system comprises a target system.

22. The communication system of claim 20, wherein said system cycle comprises an emulation cycle.

23. A method for exchanging communication signals between a hardware logic emulation system and a target system, the hardware logic emulation system having a plurality of programmable logic devices or processor chips, the target system verifying a logic design being emulated by the hardware logic emulation system, the method comprising:

receiving a system clock signal and a synchronization signal from the hardware logic emulation system, said synchronization signal initiating an emulation cycle that comprises a predetermined number of system clock cycles of said system clock signal;

receiving output data signals from the hardware logic emulation system via a plurality of output data connections, said output data signals being dynamic during said emulation cycle;

providing input data signals to the hardware logic emulation system via a plurality of input data connections, said input data signals being dynamic during said emulation cycle;

exchanging target data signals with the target system via a plurality of reconfigurable bidirectional connections, said target data signals being dynamic during said emulation cycle;

configuring at least one of a plurality of field programmable gate arrays according to configuration information stored in a configuration memory space to couple a first reconfigurab1e portion of the plurality of input data connections and a first reconfigurable portion of the plurality of reconfigurable bidirectional connections, and to couple a first reconfigurable portion of the plurality of output data connections and the first reconfigurable portion of the plurality of reconfigurable bidirectional connections;

reconfigurably scheduling exchange of the target data signals between the hardware emulation logic and the target system according to the configuration information,

wherein at least one reconfigurable bidirectional connection of said reconfigurable bidirectional connections is configurable to change its configuration between providing outgoing target data signals and receiving incoming target data signals during said emulation cycle.

24. The method of claim 23,

further comprising:

sampling first and second output data signals from the plurality of output data connections during a first system clock cycle of said emulation cycle; and

providing said first and second sampled output data signals to a selected reconfigurable bidirectional connection of the plurality of reconfigurable bidirectional connections, said second sampled output data signal comprising a control signal and determining whether said selected reconfigurable bidirectional connection provides said first sampled output data signal to the target system during a second system clock cycle of said emulation cycle.

25. The method of claim 23,

further comprising:

sampling a first output data signal from a selected output data connection of the plurality output data connections during a first system clock cycle of said emulation cycle;

sampling a second output data signal from said selected output data connection of the plurality output data connections during said second system clock cycle of said emulation cycle, and

providing said first and second sampled output data signals to a selected reconfigurable bidirectional connection of the plurality of reconfigurable bidirectional connections, said second sampled output data signal comprising a control signal and determining whether said selected reconfigurable bidirectional connection provides said first sampled output data signal to the target system during a third system clock cycle of said emulation cycle.

26. The method of claim 23,

further comprising:

sampling an incoming first target data signal received via a selected reconfigurable bidirectional connection of the plurality of reconfigurable bidirectional connections during a first system clock cycle of said emulation cycle;

sampling an incoming second target data signal received via said selected reconfigurable bidirectional connection of the plurality of reconfigurable bidirectional connections during a second system clock cycle of said emulation cycle, and

providing said first and second input data signals to the hardware logic emulation system via first and second input data connections of the plurality of input data connections during a third system clock cycle of said emulation cycle.

27. The method of claim 26, wherein said first and second system clock cycles comprise different clock cycles of said emulation cycle.

28. The method of claim 27, wherein said second system clock cycle is disposed in time between said first and third system clock cycles.

29. The method of claim 26, wherein said second and third system clock cycles comprise the same system clock cycle.

30. The method of claim 26, further comprising storing at least one of said sampled first and second output data signals.

31. The method of claim 27,

further comprising:

sampling first and second incoming target data signals received via the plurality of bidirectional connections during a first system clock cycle of said emulation cycle;

providing said first sampled target data signal to the hardware logic emulation system via a selected input data connection of the plurality of input data connections during a second system clock cycle of said emulation cycle; and

providing said second sampled target data signal to the hardware logic emulation system via said selected input data connection of the plurality of input data connections during a third system clock cycle of said emulation cycle.

32. The method of claim 31, wherein said second and third system clock cycles comprise different clock cycles of said emulation cycle.

33. The method of claim 32, wherein said second system clock cycle is disposed in time between said first and third system clock cycles.

34. The method of claim 31, wherein said first and second system clock cycles comprise the same system clock cycle.

35. The method of claim 31, further comprising storing at least one of said sampled first and second output data signals.