High-performance, superscalar-based computer system with out-of-order instruction execution

• US 7,721,070 B2
• Filed: 09/22/2008
• Issued: 05/18/2010
• Est. Priority Date: 07/08/1991
• Status: Expired due to Fees

• Current Assignee: Derek J. Lentz, Johannes Wang, Le Trong Nguyen, Quang H. Trang, Sanjiv Garg, Sze-Shun Wang, Te-Li Lau, Yasuaki Hagiwara, Yoshiyuki Miyayama
• Original Assignee: Derek J. Lentz, Johannes Wang, Le Trong Nguyen, Quang H. Trang, Sanjiv Garg, Sze-Shun Wang, Te-Li Lau, Yasuaki Hagiwara, Yoshiyuki Miyayama
• Inventors: Wang, Johannes, Wang, Sze-Shun, Nguyen, Le Trong, Miyayama, Yoshiyuki, Trang, Quang H., Lau, Te-Li, Garg, Sanjiv, Lentz, Derek J., Hagiwara, Yasuaki
• Primary Examiner(s): Li; Aimee J
• Application Number:
  US12/235,215
• Publication Number:
  US 20090019261A1
• Time in Patent Office: 603 Days
• Field of Search: 712/205, 712/207, 712/208, 712/212, 712/215, 712/216
• US Class Current: 712/215
• CPC Class Codes: G06F 9/30061 Multi-way branch instructions, e.g. CASE
• CPC Class Codes: G06F 9/30072 to perform conditional operations, e.g. using predicates or guards
• CPC Class Codes: G06F 9/30112 comprising data of variable length
• CPC Class Codes: G06F 9/30116 Shadow registers, e.g. coupled registers, not forming part of the register space
• CPC Class Codes: G06F 9/30123 according to context, e.g. thread buffers
• CPC Class Codes: G06F 9/3013 according to data content, e.g. floating-point registers, address registers
• CPC Class Codes: G06F 9/30134 Register stacks; shift registers
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/327 for interrupts
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/3804 for branches, e.g. hedging, branch folding
• CPC Class Codes: G06F 9/3806 using address prediction, e.g. return stack, branch history buffer
• CPC Class Codes: G06F 9/3822 Parallel decoding, e.g. parallel decode units
• CPC Class Codes: G06F 9/3826 Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
• CPC Class Codes: G06F 9/3834 Maintaining memory consistency
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3838 Dependency mechanisms, e.g. register scoreboarding
• CPC Class Codes: G06F 9/384 Register renaming
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3856 Reordering of instructions, e.g. using queues or age tags
• CPC Class Codes: G06F 9/3858 : Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/3863 : using multiple copies of the architectural state, e.g. shadow registers
• CPC Class Codes: G06F 9/3865 : using deferred exception handling, e.g. exception flags
• CPC Class Codes: G06F 9/3885 : using a plurality of independent parallel functional units

Abstract

A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

Claims

1. A computer system comprising:

a memory;

a superscalar microprocessor; and

a bus coupled between the memory and the superscalar microprocessor, wherein the superscalar microprocessor comprises

an instruction fetch unit configured to fetch instructions from an instruction store according to a sequential program order, and

an instruction execution unit configured to concurrently receive a set of from one to a maximum number (N) of instructions from the instruction fetch unit, the instruction execution unit including

an instruction buffer configured to store instruction information for each instruction received from the instruction fetch unit, wherein the instruction buffer has sufficient capacity to store the instruction information for at least twice the number N of instructions,

a register file comprising a plurality of temporary buffers and a plurality of retired registers, wherein the temporary buffers are arranged in a plurality of groups of temporary buffers, each group of temporary buffers including N of the temporary buffers,

renaming logic configured to concurrently establish an association between each instruction in a set of instructions concurrently received from the instruction fetch unit and a respective one of the temporary buffers in a selected one of the groups of temporary buffers, wherein a position of each instruction within the set of instructions determines which one of the temporary buffers in the selected group of temporary buffers is associated with that instruction,

a plurality of functional units configured to execute instructions, thereby generating result data,

an issue control circuit configured to concurrently issue more than one of the instructions for which instruction information is stored in the instruction buffer to the functional units for execution, the issue control circuit being further configured to issue at least some of the instructions out of the sequential program order,

a plurality of data routing paths coupled between the functional units and the register file and configured to transfer result data from more than one of the functional units to the temporary buffers concurrently, and

retirement control logic coupled to the register file and configured to retire instructions according to the sequential program order, wherein the retirement control logic is further configured to concurrently retire all of the instructions in a set of instructions after all of the instructions in that set of instructions have completed.

2. The computer system of claim 1, wherein the retirement control logic is further configured to concurrently retire all of the instructions in a set of instructions after all of the instructions in the set of instructions have completed and all instructions that precede the set of instructions according to the sequential program order have been retired.

3. The computer system of claim 1, wherein the retirement control logic is further configured such that retiring all of the instructions in a set of instructions includes transferring the result data from the temporary buffers in the group of temporary buffers associated with the set of instructions to selected ones of the retired registers.

4. The computer system of claim 3, wherein the temporary buffers are configured as a FIFO and wherein each group of temporary buffers corresponds to an entry in the FIFO.

5. The computer system of claim 4, wherein the retirement control logic is further configured to advance the FIFO by one group of temporary buffers upon retirement of each set of instructions.

6. The computer system of claim 1, wherein:

the instruction information stored in the instruction buffer includes an identifier of one of the retired registers; and

the retirement control logic is further configured such that retiring all of the instructions in the set of instructions includes transferring the result data for at least one of the instructions in the set of instructions from the temporary buffer associated with that instruction to the one of the retired registers identified by a retired register identifier stored for that instruction.

7. The computer system of claim 1, wherein the instruction buffer is configured as a FIFO and wherein each entry in the FIFO has sufficient capacity to store instruction information for N instructions.

8. The computer system of claim 1, wherein the instruction information stored in the instruction buffer includes information indicating an operation to be performed.

9. The computer system of claim 1, wherein the instruction buffer has the capacity to store the instruction information for exactly twice the number N of instructions.

10. The computer system of claim 1, wherein the number of temporary buffers is equal to the number of instructions for which the instruction buffer has the capacity to store the instruction information.

11. The computer system of claim 1, wherein N is four.

12. The computer system of claim 1, wherein the instruction execution unit further includes:

a decode circuit configured to concurrently decode all of the instructions in a set of instructions concurrently received by the instruction execution unit.

13. The computer system of claim 12, wherein the decode circuit is disposed at a pipeline stage subsequent to a stage at which the instruction information for a set of instructions is stored into the instruction buffer.

14. The computer system of claim 1, further comprising:

bypass control logic coupled to the plurality of data routing paths and configured to supply result data from one of the functional units as operand data for another one of the functional units via an alternate data path that bypasses the register file.

15. The computer system of claim 14, wherein supplying the result data via the alternate data path occurs concurrently with transferring the result data to the temporary buffers.

16. The computer system of claim 1, further comprising:

a register rename circuit configured to concurrently identify, for each instruction in a set of instructions concurrently received by the instruction execution unit, a register file entry corresponding to a source of an operand for the instruction.

17. The computer system of claim 16, wherein the register rename circuit is further configured to concurrently identify a register file entry corresponding to a source of an operand for each of a first instruction and a second instruction in a set of instructions wherein the second instruction has a data dependency on the first instruction.

18. The computer system of claim 1, wherein the instruction fetch unit is further configured to provide a new set of instructions to the instruction execution unit in response to a previous set of instructions being retired.

19. The computer system of claim 1, wherein:

the instruction fetch unit includes a branch prediction circuit configured to detect a first conditional branch instruction among the instructions fetched from the instruction store and to predict whether a first conditional branch corresponding to the first conditional branch instruction will be taken or not taken, and

the instruction fetch unit is further configured to deliver instructions subsequent to the first conditional branch instruction to the instruction execution unit based on the prediction.

20. The computer system of claim 19, wherein:

the branch prediction circuit is further configured to detect a second conditional branch instruction among the instructions fetched from the instruction store and to predict, prior to a determination of whether the first conditional branch was correctly predicted, whether a second conditional branch corresponding to the second conditional branch instruction will be taken or not taken, and

the instruction fetch unit is further configured to deliver instructions subsequent to the second conditional branch instruction to the instruction execution unit based on the prediction as to the second conditional branch.

21. The computer system of claim 20, wherein the instruction fetch unit is further configured to continue delivering instructions to the instruction execution unit as long as the instruction buffer is not filled with sets of instructions, regardless of the number of conditional branch instructions that have been previously delivered to the instruction execution unit but not retired.