Implementation of thermal throttling logic
First Claim
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1. A computer implemented method for implementing thermal throttling logic in a heterogeneous multi-core processor that is implemented on a single integrated circuit chip, comprising:
- providing, in each one of a plurality of cores that are included in the heterogeneous multi-core processor, a separate digital thermal sensor that senses a temperature in the digital thermal sensor'"'"'s respective one of the plurality of cores;
setting, in a throttle point register that is included in the processor and outside of the plurality of cores, a first throttling temperature that is used for a first one of the plurality of cores and a second throttling temperature that is used for a second one of the plurality of cores, wherein the first and second throttling temperatures are used at the same time;
receiving a sensed temperature value from a particular digital thermal sensor representing a particular current temperature of a particular one of the plurality of cores;
reporting the sensed temperature as the particular current temperature in a current temperature status register; and
responsive to the particular current temperature exceeding a particular throttling temperature of the particular one of the plurality of cores, throttling only the particular one of the plurality of cores.
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Abstract
A computer implemented method, data processing system, and processor are provided for implementation of thermal throttling logic. A sensed temperature value is received from a digital thermal sensor representing a current temperature of a unit associated with the digital thermal sensor in the integrated circuit. The sensed temperature is reported as the current temperature in a status register. The unit in the integrated circuit is throttled in response to the current temperature exceeding a first predetermined value.
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Citations
18 Claims
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1. A computer implemented method for implementing thermal throttling logic in a heterogeneous multi-core processor that is implemented on a single integrated circuit chip, comprising:
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providing, in each one of a plurality of cores that are included in the heterogeneous multi-core processor, a separate digital thermal sensor that senses a temperature in the digital thermal sensor'"'"'s respective one of the plurality of cores; setting, in a throttle point register that is included in the processor and outside of the plurality of cores, a first throttling temperature that is used for a first one of the plurality of cores and a second throttling temperature that is used for a second one of the plurality of cores, wherein the first and second throttling temperatures are used at the same time; receiving a sensed temperature value from a particular digital thermal sensor representing a particular current temperature of a particular one of the plurality of cores; reporting the sensed temperature as the particular current temperature in a current temperature status register; and responsive to the particular current temperature exceeding a particular throttling temperature of the particular one of the plurality of cores, throttling only the particular one of the plurality of cores. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A data processing system comprising:
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a bus; a memory coupled to the bus, wherein the memory includes a set of instructions; and a single integrated circuit chip on which is implemented a heterogeneous multi-core processor, wherein the processor is coupled to the bus, and wherein a separate digital thermal sensor is provided in each one of a plurality of cores that are included in the heterogeneous multi-core processor, wherein the separate digital thermal sensor senses a temperature in the digital thermal sensor'"'"'s respective one of the plurality of cores; and
further wherein the processor executes the set of instructions to;set, in a throttle point register that is included in the processor and outside of the plurality of cores, a first throttling temperature that is used for a first one of the plurality of cores and a second throttling temperature that is used for a second one of the plurality of cores, wherein the first and second throttling temperatures are used at the same time; receive a sensed temperature value from a particular digital thermal sensor representing a particular current temperature of a particular one of the plurality of cores; report the sensed temperature as the particular current temperature in a current temperature status register; and responsive to the particular current temperature exceeding a particular throttling temperature of the particular one of the plurality of cores, throttle only the particular one of the plurality of cores. - View Dependent Claims (12, 13, 14)
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15. A heterogeneous multi-core processor that is implemented on a single integrated circuit chip, comprising:
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a plurality of cores, wherein each one of the plurality of cores includes a separate digital thermal sensor that senses a temperature in the digital thermal sensor'"'"'s respective one of the plurality of cores; a throttle point register that is included in the processor and outside of the plurality of cores in which is set a first throttling temperature that is used for a first one of the plurality of cores and a second throttling temperature that is used for a second one of the plurality of cores, wherein the first and second throttling temperatures are used at the same time; a thermal management control state machine; a comparator; and a digital thermal sensor, wherein the processor executes a set of instructions to; receive a sensed temperature value from a particular digital thermal sensor representing a particular current temperature of a particular one of the plurality of cores; report, using the state machine, the sensed temperature as the particular current temperature in a current temperature status register; and throttle, using the state machine, only the particular one of the plurality of cores responsive to the particular current temperature exceeding a particular throttling temperature of the particular one of the plurality of cores. - View Dependent Claims (16, 17, 18)
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Specification