Method and apparatus for reducing clock frequency during low workload periods

• US 7,721,129 B2
• Filed: 01/12/2006
• Issued: 05/18/2010
• Est. Priority Date: 09/30/2002
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kazachinsky, Itamar S., Orenstein, Doron
• Primary Examiner(s): Lee; Thomas
• Assistant Examiner(s): Chang; Eric
• Application Number:
  US11/330,647
• Publication Number:
  US 20060129860A1
• Time in Patent Office: 1,587 Days
• Field of Search: 713/323
• US Class Current: 713/323
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A clock frequency control unit for an integrated circuit (IC) includes a clock generator, a finite state machine (FSM), and a gating circuit (GC). The FSM has at least first and second states corresponding to non-low workload low workload states, respectively. In the first state, the GC provides a clock signal to functional units of the IC with the same frequency as the clock generator output. In the second state, the GC reduces the frequency of the clock signal. In one embodiment, the GC masks out selected cycles of the clock generator output to reduce the clock signal frequency. The FSM monitors the operation of the IC to transition from the first state to the second state when selected “low workload” conditions are detected (e.g., long latency cache miss). Similarly, the FSM transitions from the second state to the first state when selected “non-low workload” conditions are detected.

Claims

1. A method comprising:

when a processor is operating in a first state, monitoring the processor'"'"'s operation for a first set of selected conditions, the processor having a plurality of functional units, the plurality of functional units receiving a clock signal with a first frequency when the processor is operating in the first state, the first set of selected conditions being indicative of a low workload period in the processor;

selecting a grace period from a plurality of programmable grace periods based on detecting which one of the first set of selected conditions is satisfied, wherein each of the plurality of programmable grace periods stores a different grace period to allow completion or processing of a different event;

waiting for the selected grace period to expire after detecting that the one of the first set of selected conditions is satisfied; and

causing the processor to operate in a second state after expiration of the selected grace period, wherein in the second state the clock signal has a second frequency that is less than the first frequency, wherein one of the plurality of programmable grace periods is used to allow one or more pending store operations to be processed prior to the processor operating in the second state.

2. The method of claim 1, further comprising:

when the processor is operating in the second state, monitoring the processor operation for a second set of selected conditions, the second set of selected conditions being indicative of the termination of the low workload period; and

causing the processor to operate in the first state when the second set of selected conditions is satisfied.

3. The method of claim 2, wherein the first set of selected conditions includes:

a cache miss signal being asserted by a level two cache.

4. The method of claim 2, wherein the second set of selected conditions comprises a signal indicating that the level two cache is ready for a memory transaction.

5. The method of claim 2, wherein one of the plurality of programmable grace periods is selected to allow the processor to complete an arithmetic operation.

6. The method of claim 5, wherein the arithmetic operation is a multiply or a divide operation.

7. The method of claim 2, wherein the second set of selected conditions comprises a receipt of a snoop request.

8. The method of claim 2, wherein the second set of selected conditions comprises assertion of an interrupt signal.

9. The method of claim 2, wherein the second set of selected conditions comprises assertion of a reset signal.

10. The method of claim 2, wherein the second set of selected conditions comprises assertion of a stop clock signal.

11. The method of claim 1, wherein one of the plurality of programmable grace periods is selected to allow operations waiting in one or more reservation stations to be executed.