Method of timing calibration using slower data rate pattern

• US 7,721,135 B2
• Filed: 12/12/2007
• Issued: 05/18/2010
• Est. Priority Date: 11/09/2000
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Round Rock Research LLC
• Inventors: Jeddeloh, Joseph M., Ryan, Kevin J., Lee, Terry R.
• Primary Examiner(s): Du; Thuan N
• Application Number:
  US12/000,434
• Publication Number:
  US 20080098253A1
• Time in Patent Office: 888 Days
• Field of Search: 713/400, 713/401, 713/503, 713/601, 714/814, 714/731
• US Class Current: 713/401
• CPC Class Codes: G01R 31/31937 Timing aspects, e.g. measuring propagation delay G01R31/3191 and G01R31/31922 take precedence; marginal testing G06F11/24
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/023 in clock generator or timing circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50012 of timing
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1087 Data input latches
• CPC Class Codes: G11C 7/109 Control signal input circuits
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: H03L 7/0812 and where no voltage or current controlled oscillator is used
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled

Abstract

An improved technique and associated apparatus for timing calibration of a logic device is provided. A calibration test pattern is transferred to a logic device first at a data rate slower than normal operating speed to ensure correct capture of the pattern at the device to be calibrated. Once the pattern is correctly captured and stored, the test pattern is transmitted to the logic device at the normal operating data rate to perform timing calibration. The improved technique and apparatus permits the use of any pattern of bits as a calibration test pattern, programmable by the user or using easily-interchangeable hardware.

Claims

1. An apparatus comprising:

a receiving circuit for receiving a calibration bit pattern at a digital circuit, the digital circuit also receiving incoming data;

a memory device for storing the received calibration bit pattern; and

an adjusting circuit for using the stored calibration pattern during subsequent calibration operations to adjust a relative timing of clock and data signals on at least one data path of the digital circuit to produce a reliable detection of the calibration bit pattern,

wherein the receiving circuit receives the calibration bit pattern at a first data rate which is lower than a data rate at which the digital circuit receives incoming data.

2. The apparatus of claim 1, wherein the reliable detection of the calibration bit pattern is performed at a data rate approximately equal to the data rate at which the digital circuit receives incoming data.

3. The apparatus of claim 2, wherein the data rate at which the digital circuit receives incoming data is about an integer number of times as fast as the first data rate.

4. The apparatus of claim 1, wherein the receiving circuit comprises a circuit for lowering a frequency of a clock signal used to synchronize data received by the receiving circuit.

5. The apparatus of claim 1, further comprising:

a locked loop circuit for delaying a control signal; and

a deactivating circuit for deactivating the locked loop circuit at least during receiving of the calibration bit pattern.

6. The apparatus of claim 5, wherein the locked loop circuit comprises a delay locked loop (DLL) circuit.

7. The apparatus of claim 5, wherein the locked loop circuit comprises a phase locked loop (PLL) circuit.

8. The apparatus of claim 1, wherein the memory device stores only every Nth bit of data received.

9. The apparatus of claim 8, wherein N=4.