Optimized reed-solomon decoder

• US 7,721,185 B1
• Filed: 01/09/2006
• Issued: 05/18/2010
• Est. Priority Date: 03/23/2005
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Feng, Weishi
• Primary Examiner(s): Chaudry; Mujtaba K
• Assistant Examiner(s): Ahmed; Enam
• Application Number:
  US11/327,934
• Time in Patent Office: 1,590 Days
• Field of Search: 714/784
• US Class Current: 714/784
• CPC Class Codes: H03M 13/1515 Reed-Solomon codes
• CPC Class Codes: H03M 13/1525 Determination and particular use of error location polynomials
• CPC Class Codes: H03M 13/153 using the Berlekamp-Massey algorithm
• CPC Class Codes: H03M 13/154 Error and erasure correction, e.g. by using the error and erasure locator or Forney polynomial
• CPC Class Codes: H03M 13/1565 Decoding beyond the bounded minimum distance [BMD]
• CPC Class Codes: H03M 13/3707 Adaptive decoding and hybrid decoding, e.g. decoding methods or techniques providing more than one decoding algorithm for one code
• CPC Class Codes: H03M 13/3746 with iterative decoding

Abstract

An error decoding system that comprises a first Reed-Solomon (RS) decoder that receives an encoded codeword and generates a decoded codeword. An inner code (IC) decoder checks the decoded codeword for uncorrected errors. A decoding control module communicates with the first RS decoder and the IC decoder, iteratively modifies a parameter of the first RS decoder if the IC decoder detects uncorrected errors in the decoded codeword, and instructs the first RS decoder to decode the encoded codeword again after modifying the parameter.

Claims

1. An error decoding system comprising:

a first Reed-Solomon (RS) decoder that receives an encoded codeword and generates a decoded codeword;

an inner code (IC) decoder that checks said decoded codeword for uncorrected errors; and

a decoding control module that communicates with said first RS decoder and said IC decoder, that iteratively modifies an error burst length of said first RS decoder if said IC decoder detects uncorrected errors in said decoded codeword, and that instructs said first RS decoder to decode said encoded codeword again after modifying said error burst length.

2. The error decoding system of claim 1 wherein said IC decoder includes at least one of a cyclic redundancy check module and a checksum computation module.

3. The error decoding system of claim 1 wherein said encoded codeword comprises a plurality of data symbols and C check symbols, and said first RS decoder is capable of correcting x random errors when 2x+n<

C, where n is said error burst length.

4. The error decoding system of claim 1 wherein said decoding control module varies said error burst length over a range of values.

5. The error decoding system of claim 4 wherein said decoding control module varies said error burst length by multiples of two.

6. The error decoding system of claim 4 wherein said decoding control module repeatedly instructs said first RS decoder to decode said encoded codeword until the occurrence of at least one of said IC decoder detects no uncorrected errors in said decoded codeword and said decoding control module reaches an end of said range of values.

7. The error decoding system of claim 4 wherein said decoding control module varies said error burst length between a first value and a second value until said IC decoder detects no uncorrected errors.

8. The error decoding system of claim 7 wherein said first value is greater than said second value.

9. The error decoding system of claim 7 wherein said encoded codeword comprises a plurality of data symbols and C check symbols, and wherein said first value is less than or equal to C−

3.

10. The error decoding system of claim 7 wherein said second value is greater than or equal to 3.

11. The error decoding system of claim 1 further comprising a second Reed-Solomon (RS) decoder that generates a second decoded codeword from said encoded codeword, wherein if said IC decoder detects no uncorrected errors in said second decoded codeword, said decoding control module instructs said first RS decoder to remain idle.

12. The error decoding system of claim 11 wherein said encoded codeword comprises a plurality of data symbols and 2t check symbols, and said second RS decoder is capable of correcting up to x errors and y erasures when 2x+y≦

2t.

13. The error decoding system of claim 12 wherein said second RS decoder includes said first RS decoder operating in a specific operating mode.

14. A communications system comprising:

the error decoding system of claim 1;

an encoding system including an inner code (IC) encoder and a Reed-Solomon (RS) encoder, wherein said IC encoder receives user data, encodes said user data with error checking information into a first codeword, and transmits said first codeword to said RS encoder, and wherein said RS encoder generates an encoded codeword from said first codeword; and

a communications channel that receives said encoded codeword and transmits said encoded codeword to said error decoding system.

15. The communications system of claim 14 wherein said IC encoder appends a calculated value to said user data to form said first codeword.

16. The communications system of claim 15 wherein said IC decoder calculates a second value from said decoded codeword, and determines that said decoded codeword contains uncorrected errors if said second value is not equal to said appended calculated value.

17. An error decoding method comprising:

receiving an encoded codeword;

generating a decoded codeword using Reed-Solomon (RS) decoding;

checking said decoded codeword for uncorrected errors; and

iteratively modifying an error burst length of said RS decoding if uncorrected errors are detected in said decoded codeword.

18. The error decoding method of claim 17 wherein said checking said decoded codeword includes calculating at least one of a cyclic redundancy check and a checksum.

19. The error decoding method of claim 17 wherein said encoded codeword comprises a plurality of data symbols and C check symbols, and wherein said generating said decoded codeword includes correcting up to x random errors where 2x+n<

C, where n is said error burst length.

20. The error decoding method of claim 17 wherein said iteratively modifying said error burst length includes varying said error burst length over a range of values.

21. The error decoding method of claim 20 wherein said iteratively modifying said error burst length includes varying said error burst length by multiples of two.

22. The error decoding method of claim 20 further comprising repeating said generating said decoded codeword until the occurrence of at least one no uncorrected errors are detected in said decoded codeword and an end of said range of values is reached.

23. The error decoding method of claim 20 wherein said iteratively modifying said error burst length includes varying said error burst length from a first value through a second value until no uncorrected errors are detected.

24. The error decoding method of claim 23 wherein said first value is greater than said second value.

25. The error decoding method of claim 23 wherein said encoded codeword comprises a plurality of data symbols and C check symbols, and wherein said first value is less than or equal to C−

3.

26. The error decoding method of claim 23 wherein said second value is greater than or equal to 3.