Method and system for allowing code to be securely initialized in a computer
First Claim
1. One or more computer storage media having stored thereon a plurality of instructions that, when executed by one or more processors of a computer, causes the one or more processors to perform acts including:
- allowing operation of the computer to begin based on untrusted code;
loading, under control of the untrusted code, a trusted core into memory;
preventing each of one or more central processing units and each of one or more bus masters in the computer from accessing the memory;
resetting each of the one or more central processing units;
after resetting, allowing one central processing unit to access the memory and execute trusted core code beginning at a first instruction, wherein the first instruction is for execution of the trusted core at a beginning of the trusted core; and
after allowing the one central processing unit to access the memory, allowing any other central processing units and any bus masters in the computer to access the memory and execute the trusted core code beginning at a different instruction than the first instruction, wherein the different instruction is for execution of the trusted core at a location independent of the beginning of the trusted core.
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Accused Products
Abstract
A memory controller prevents CPUs and other I/O bus masters from accessing memory during a code (for example, trusted core) initialization process. The memory controller resets CPUs in the computer and allows a CPU to begin accessing memory at a particular location (identified to the CPU by the memory controller). Once an initialization process has been executed by that CPU, the code is operational and any other CPUs are allowed to access memory (after being reset), as are any other bus masters (subject to any controls imposed by the initiated code).
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Citations
20 Claims
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1. One or more computer storage media having stored thereon a plurality of instructions that, when executed by one or more processors of a computer, causes the one or more processors to perform acts including:
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allowing operation of the computer to begin based on untrusted code; loading, under control of the untrusted code, a trusted core into memory; preventing each of one or more central processing units and each of one or more bus masters in the computer from accessing the memory; resetting each of the one or more central processing units; after resetting, allowing one central processing unit to access the memory and execute trusted core code beginning at a first instruction, wherein the first instruction is for execution of the trusted core at a beginning of the trusted core; and after allowing the one central processing unit to access the memory, allowing any other central processing units and any bus masters in the computer to access the memory and execute the trusted core code beginning at a different instruction than the first instruction, wherein the different instruction is for execution of the trusted core at a location independent of the beginning of the trusted core. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method comprising:
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allowing a computer to begin operation based on untrustworthy code; loading, under the control of the untrustworthy code, additional code into memory; and initiating execution of the additional code in a secure manner despite the untrustworthy code in the computer, the initiating including; receiving a read request corresponding to a central processing unit reset vector from a first central processing unit of the computer; using an association between the central processing unit reset vector and an initialization vector for the additional code to return, in response to the read request, the initialization vector rather than the processor reset vector; and allowing access to the memory beginning with the initialization vector. - View Dependent Claims (11, 12, 13, 14, 15, 16)
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17. A memory controller comprising:
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a first interface to allow communication with a processor; a second interface to allow communication with a system memory; and a controller, coupled to the first interface and the second interface, to reset the processor, to allow the processor to execute a code initialization process beginning at a first instruction while preventing any other processors coupled to the memory controller from accessing the system memory, and to subsequently allow any of the other processors to access the system memory beginning at a second instruction that is different than the first instruction, wherein the first instruction is for execution of a trusted core at a beginning of the trusted core and the second instruction is for execution of the trusted core at a location independent of the beginning of the trusted core. - View Dependent Claims (18, 19, 20)
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Specification