Method and system for allowing code to be securely initialized in a computer

• US 7,721,341 B2
• Filed: 06/15/2005
• Issued: 05/18/2010
• Est. Priority Date: 11/22/2000
• Status: Expired due to Term

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Corporation
• Inventors: Willman, Bryan, England, Paul
• Primary Examiner(s): Moise; Emmanuel L
• Assistant Examiner(s): Teslovich; Tamara
• Application Number:
  US11/152,909
• Publication Number:
  US 20050235166A1
• Time in Patent Office: 1,798 Days
• Field of Search: 380/259, 713 1- 2, 713/164, 713187-190, 713192-194, 726/27, 726/30
• US Class Current: 726/27
• CPC Class Codes: G06F 15/177 Initialisation or configuration control processor initialisation G06F9/4405
• CPC Class Codes: G06F 21/575 Secure boot
• CPC Class Codes: G06F 9/4405 Initialisation of multiprocessor systems

Abstract

A memory controller prevents CPUs and other I/O bus masters from accessing memory during a code (for example, trusted core) initialization process. The memory controller resets CPUs in the computer and allows a CPU to begin accessing memory at a particular location (identified to the CPU by the memory controller). Once an initialization process has been executed by that CPU, the code is operational and any other CPUs are allowed to access memory (after being reset), as are any other bus masters (subject to any controls imposed by the initiated code).

Claims

1. One or more computer storage media having stored thereon a plurality of instructions that, when executed by one or more processors of a computer, causes the one or more processors to perform acts including:

allowing operation of the computer to begin based on untrusted code;

loading, under control of the untrusted code, a trusted core into memory;

preventing each of one or more central processing units and each of one or more bus masters in the computer from accessing the memory;

resetting each of the one or more central processing units;

after resetting, allowing one central processing unit to access the memory and execute trusted core code beginning at a first instruction, wherein the first instruction is for execution of the trusted core at a beginning of the trusted core; and

after allowing the one central processing unit to access the memory, allowing any other central processing units and any bus masters in the computer to access the memory and execute the trusted core code beginning at a different instruction than the first instruction, wherein the different instruction is for execution of the trusted core at a location independent of the beginning of the trusted core.

2. One or more computer storage media as recited in claim 1, wherein the one or more processors comprise one or more controllers of one or more memory controllers.

3. One or more computer storage media as recited in claim 1, wherein the preventing comprises preventing each of the one or more central processing units and each of the one or more bus masters from accessing the memory in response to an initialize trusted core command received from one of the one or more central processing units.

4. One or more computer storage media as recited in claim 1, wherein the loading the trusted core comprises copying different parts of the trusted core from one or more sources and combining the different parts to assemble the trusted core.

5. One or more computer storage media as recited in claim 4, wherein combining the different parts comprises exclusive-ORing bits of the different parts.

6. One or more computer storage media as recited in claim 1, wherein the plurality of instructions further cause the one or more processors to perform acts including:

extracting a cryptographic measure of the trusted core in the memory; and

storing the extracted cryptographic measure.

7. One or more computer storage media as recited in claim 6, wherein the plurality of instructions further cause the one or more processors to perform acts including:

resetting a cryptographic processor;

requesting the cryptographic processor to extract the cryptographic measure; and

receiving the extracted cryptographic measure from the cryptographic processor.

8. One or more computer storage media as recited in claim 1, wherein the resetting comprises asserting, on a processor bus, a RESET#signal to each of the one or more central processing units.

9. One or more computer storage media as recited in claim 1, wherein the resetting comprises clearing a state of each of the one or more central processing units.

10. A method comprising:

allowing a computer to begin operation based on untrustworthy code;

loading, under the control of the untrustworthy code, additional code into memory; and

initiating execution of the additional code in a secure manner despite the untrustworthy code in the computer, the initiating including;

receiving a read request corresponding to a central processing unit reset vector from a first central processing unit of the computer;

using an association between the central processing unit reset vector and an initialization vector for the additional code to return, in response to the read request, the initialization vector rather than the processor reset vector; and

allowing access to the memory beginning with the initialization vector.

11. A method as recited in claim 10, wherein the initiating further comprises initiating execution of the additional code in a secure manner despite both the untrustworthy code in the computer and other pre-existent state of the computer.

12. A method as recited in claim 10, wherein the initiating execution of the additional code in a secure manner comprises:

preventing each of one or more central processing units in the computer from accessing the memory;

preventing each of one or more bus masters in the computer from accessing the memory;

resetting each of the one or more central processing units;

allowing the first central processing unit to access the memory and execute a code initialization process; and

after execution of the code initialization process, allowing any other central processing units and any of the one or more bus masters to access the memory.

13. A method as recited in claim 10, wherein the initiating comprises initiating execution of the additional code in a secure manner without requiring any additional bus transactions to be supported by the first central processing unit.

14. A method as recited in claim 10, further comprising:

remapping the additional code to appear at an address where the first central processing unit starts executing after being reset.

15. A method as recited in claim 10, further comprising:

receiving, from a second central processing unit of the computer, a second read request corresponding to the central processing unit reset vector;

responding to the second read request with instructions to cause the central processing unit to begin executing the additional code at a different instruction than the first central processing unit began executing the additional code.

16. A method as recited in claim 10, wherein the loading the additional code comprises copying different portions of the additional code from a plurality of different sources including one or more of:

a local mass storage device, a remote device, and a local chipset.

17. A memory controller comprising:

a first interface to allow communication with a processor;

a second interface to allow communication with a system memory; and

a controller, coupled to the first interface and the second interface, to reset the processor, to allow the processor to execute a code initialization process beginning at a first instruction while preventing any other processors coupled to the memory controller from accessing the system memory, and to subsequently allow any of the other processors to access the system memory beginning at a second instruction that is different than the first instruction, wherein the first instruction is for execution of a trusted core at a beginning of the trusted core and the second instruction is for execution of the trusted core at a location independent of the beginning of the trusted core.

18. A memory controller as recited in claim 17, wherein the controller is further to allow the processor to execute the code initialization process while preventing any bus masters from accessing the system memory.

19. A memory controller as recited in claim 17, wherein the controller is further to:

reset any other processor coupled to the memory controller prior to allowing the processor to execute the code initialization process;

prevent any other processor and any bus master coupled to the memory controller from accessing the system memory until the one process executes the code initialization process; and

after execution of the code initialization process, allow any other central processing units coupled to the memory controller and any bus masters coupled to the memory controller to access the system memory beginning at the second instruction.

20. A memory controller as recited in claim 17, wherein the controller is to reset the processor by asserting, on a processor bus, a reset signal to the processor, wherein the reset signal comprises RESET#.