Package-on-package using through-hole via die on saw streets

• US 7,723,159 B2
• Filed: 06/26/2007
• Issued: 05/25/2010
• Est. Priority Date: 05/04/2007
• Status: Active Grant

• Current Assignee: JCET Semiconductor (Shaoxing) Co., Ltd.
• Original Assignee: Stats Chippac Limited
• Inventors: Do, Byung Tai, Kuan, Heap Hoe, Chow, Seng Guan
• Primary Examiner(s): Fourson; George
• Assistant Examiner(s): Parker; John M
• Application Number:
  US11/768,844
• Publication Number:
  US 20080272477A1
• Time in Patent Office: 1,064 Days
• Field of Search: 257/E21.577
• US Class Current: 438/113
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/45139 Silver (Ag) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 : the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/48472 : the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/73267 : Layer and HDI connectors
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06524 : Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/1023 : the support being an insulating substrate
• CPC Class Codes: H01L 2225/1041 : Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/1088 : Arrangements to limit the height of the assembly
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/18 : High density interconnect [HDI] connectors; Manufacturing methods related thereto interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 25/03 : all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10161 : with a rectangular active surface
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A semiconductor package-on-package (PoP) device includes a first die incorporating a through-hole via (THV) disposed along a peripheral surface of the first die. The first die is disposed over a substrate or leadframe structure. A first semiconductor package is electrically connected to the THV of the first die, or electrically connected to the substrate or leadframe structure. An encapsulant is formed over a portion of the first die and the first semiconductor package.

Claims

1. A method of forming a semiconductor device, comprising:

providing a first die incorporating a through-hole via (THV) disposed along a peripheral surface by,

(a) providing a semiconductor wafer having a plurality of die,

(b) separating the plurality of die to form a peripheral region around the plurality of die,

(c) depositing an organic material in the peripheral region around the plurality of die,

(d) forming a via in the organic material,

(e) depositing a conductive material in the via to form the THV,

(f) forming a metal trace between the THV and a bond pad on one of the plurality of die, and

(g) singulating the plurality of die through the THV to provide the first die incorporating the THV;

providing a bump disposed over a top surface of the first die, or disposed over the THV;

providing an encapsulation covering a portion of the first die and the bump;

exposing the bump by removing a portion of the encapsulation; and

stacking a second die or a first package onto the exposed bump.

2. The method of claim 1, wherein the second die further is a wire bond die.

3. The method of claim 1, wherein the first package further includes a quad flat nonlead package (QFN), a small outline nonlead package (SON), a quad flat package (QFP), a land grid array device (LGA), or a ball grid array device (BGA).

4. A method of forming a semiconductor device, comprising:

providing a semiconductor wafer having a plurality of first semiconductor die;

separating the plurality of first semiconductor die to form a peripheral region around the plurality of first semiconductor die;

depositing an organic material in the peripheral region around the plurality of first semiconductor die;

forming a via in the organic material;

depositing a conductive material in the via to form a through hole via (THV);

forming a metal trace between the THV and a bond pad on the first semiconductor die;

singulating the plurality of first semiconductor die;

forming an interconnect structure over the THV or a surface of the first semiconductor die; and

stacking a second semiconductor die or package over a first surface of the first semiconductor die, the second semiconductor die or package being electrically connected to the interconnect structure.

5. The method of claim 4, further including:

depositing an encapsulant over the first semiconductor die and interconnect structure; and

removing a portion of the encapsulant to expose the interconnect structure and electrically connect the second semiconductor die or package to the interconnect structure.

6. The method of claim 4, further including:

depositing an encapsulant over the first semiconductor die and interconnect structure; and

removing a portion of the encapsulation to expose the first semiconductor die and electrically connect the second semiconductor die or package to the first semiconductor die.

7. The method of claim 4, wherein the interconnect structure includes a bump.

8. The method of claim 4, wherein the second semiconductor die or package includes a flip chip die, quad flat nonlead package, small outline nonlead package, quad flat package, land grid array device, or ball grid array device.

9. The method of claim 4, further including stacking a third semiconductor die or package over a second surface of the first semiconductor die opposite the first surface of the first semiconductor die, the third semiconductor die or package being electrically connected to the first semiconductor die.

10. The method of claim 9, further including:

providing a substrate; and

stacking the first semiconductor die, second semiconductor die or package, and third semiconductor die or package over the substrate.

11. The method of claim 10, further including forming a bond wire to electrically connect the substrate to the first semiconductor die, second semiconductor die or package, and third semiconductor die or package.

12. A method of forming a semiconductor device, comprising:

providing a plurality of first semiconductor die separated by a peripheral region around the plurality of first semiconductor die;

depositing an organic material in the peripheral region around the first plurality of semiconductor die;

forming a conductive through hole via (THV) in the peripheral region;

forming a conductive layer between the conductive THV and a bond pad on the first semiconductor die;

forming an interconnect structure over the conductive THV or a surface of the first semiconductor die; and

stacking a second semiconductor die or package over a first surface of the first semiconductor die, the second semiconductor die or package being electrically connected to the interconnect structure.

13. The method of claim 12, further including:

depositing an encapsulant over the first semiconductor die and interconnect structure; and

removing a portion of the encapsulant to expose the interconnect structure and electrically connect the second semiconductor die or package to the interconnect structure.

14. The method of claim 12, further including:

depositing an encapsulant over the first semiconductor die and interconnect structure; and

removing a portion of the encapsulation to expose the first semiconductor die and electrically connect the second semiconductor die or package to the first semiconductor die.

15. The method of claim 12, wherein the interconnect structure includes a bump.

16. The method of claim 12, wherein the first semiconductor die or package further includes a flip chip die, quad flat nonlead package, small outline nonlead package, quad flat package, land grid array device, or ball grid array device.

17. The method of claim 12, further including stacking a third semiconductor die or package over a second surface of the first semiconductor die opposite the first surface of the first semiconductor die, the third semiconductor die or package being electrically connected to the first semiconductor die.

18. The method of claim 17, further including:

providing a substrate; and

stacking the first semiconductor die, second semiconductor die or package, and third semiconductor die or package over the substrate.

19. The method of claim 18, further including forming a bond wire to electrically connect the substrate to the first semiconductor die, second semiconductor die or package, and third semiconductor die or package.