Semiconductor device having silicide layers and method of fabricating the same
First Claim
1. A method of fabricating semiconductor devices comprising:
- forming a isolation layer in a semiconductor substrate to define an active region;
forming a gate pattern on the active region;
implanting impurities into the active region at both sides of the gate pattern;
forming a spacer insulation layer on a surface of the semiconductor substrate with the gate pattern, the spacer insulation layer having a first region between the isolation layer and the gate pattern, wherein the closer the first region lies to the gate pattern, the thinner it becomes;
anisotropically etching the spacer insulation layer to form a sidewall spacer on a sidewall of the gate pattern, and to leave a blocking insulation layer on the isolation layer and on a portion of the active region neighboring the isolation layer; and
applying a silicidation process to the semiconductor substrate to form a silicide layer on a source/drain region between the blocking insulation layer and the sidewall spacer, the silicide layer having a boundary aligned to the edge of the blocking insulation layer and a boundary aligned to the edge of the sidewall spacer.
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Abstract
Some embodiments include an isolation layer defining an active region of a substrate, a gate pattern formed on the active region, and source/drain regions formed in the active region. Sidewall spacers are formed on sidewalls of the gate pattern, and a blocking insulation layer is formed on the isolation layer and on a portion of the active region neighboring the isolation layer. A silicide layer is formed on source/drain regions between the blocking insulation layer and the sidewall spacers. Some embodiments include defining an active region of a substrate using an isolation layer, forming a gate pattern on the active region, implanting impurities into the active region, and forming a spacer insulation layer on a surface of the substrate with the gate pattern. A region of the spacer insulation layer becomes thinner the closer it is to the gate pattern. Other embodiments are described in the claims.
13 Citations
8 Claims
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1. A method of fabricating semiconductor devices comprising:
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forming a isolation layer in a semiconductor substrate to define an active region; forming a gate pattern on the active region; implanting impurities into the active region at both sides of the gate pattern; forming a spacer insulation layer on a surface of the semiconductor substrate with the gate pattern, the spacer insulation layer having a first region between the isolation layer and the gate pattern, wherein the closer the first region lies to the gate pattern, the thinner it becomes; anisotropically etching the spacer insulation layer to form a sidewall spacer on a sidewall of the gate pattern, and to leave a blocking insulation layer on the isolation layer and on a portion of the active region neighboring the isolation layer; and applying a silicidation process to the semiconductor substrate to form a silicide layer on a source/drain region between the blocking insulation layer and the sidewall spacer, the silicide layer having a boundary aligned to the edge of the blocking insulation layer and a boundary aligned to the edge of the sidewall spacer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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Specification