Three dimensional integrated circuit and method of design

• US 7,723,207 B2
• Filed: 04/19/2007
• Issued: 05/25/2010
• Est. Priority Date: 08/16/2004
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Rahman, Arifur, Kung, David S., Alam, Syed M., Guarini, Kathryn W, Elfadel, Ibrahim M., Kudva, Prabhakar N., Lavin, Mark A., Ieong, Meikei
• Primary Examiner(s): Pham; Thanh V
• Assistant Examiner(s): HENRY, CALEB E
• Application Number:
  US11/737,598
• Publication Number:
  US 20070287224A1
• Time in Patent Office: 1,132 Days
• Field of Search: 438/183, 438/455, 295/93, 257/419
• US Class Current: 438/455
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688

Abstract

A three dimensional (3D) integrated circuit (IC), 3D IC chip and method of fabricating a 3D IC chip. The chip includes multiple layers of circuits, e.g., silicon insulator (SOI) CMOS IC layers, each including circuit elements. The layers may be formed in parallel and one layer attached to another to form a laminated 3D chip.

Claims

1. A method of fabricating an integrated circuit (IC) chip, said method comprising the steps of:

a) providing an IC design;

b) placing and wiring said IC design, circuit elements being placed on at least two circuit layers, selected said circuit elements of a first circuit layer of said at least two circuit layers being wired to corresponding circuit elements on a second circuit layer of said at least two circuit layers, power up circuits for circuits on said first circuit layer being placed on said second circuit layer;

c) fabricating said at least two circuit layers;

d) attaching said second circuit layer to said first circuit layer; and

e) forming connection channels extending from circuit elements in said first circuit layer and in said second circuit layer, a three dimensional (3D) IC being formed by said circuit elements in said first circuit layer being connected to said circuit elements in said second circuit layer.

2. A method as in claim 1, wherein the step (b) of placing and wiring comprises the steps of:

i) placing a majority of circuit elements in said first circuit layer; and

ii) placing remaining circuit elements and said power up circuits on said second circuit layer.

3. A method as in claim 2, wherein the step (i) of placing a majority of elements comprises the steps of:

A) initially placing and wiring logic in said IC design on a single layer;

B) conducting performance analysis on the placed and wired said logic; and

C) placing and wiring buffers on said second circuit layer, said buffers being power up circuits.

4. A method as in claim 3, wherein the step (C) of placing and wiring includes placing and wiring selected said circuit elements originally placed on said single layer.

5. A method as in claim 2, wherein said second circuit layer is an array of circuit elements and the step (ii) of placing said remaining circuit elements comprises selecting ones from said array.

6. A method as in claim 1, wherein the step (c) of fabricating said at least two layers comprises fabricating a first of said at least two on a first silicon on insulator (SOI) wafer and a second of said at least two on a second SOI wafer.

7. A method as in claim 6, wherein the step (d) of attaching comprises the steps of:

i) attaching a glass handle wafer to said second SOI wafer;

ii) removing a substrate layer from said second SOI wafer; and

iii) attaching said second SOI wafer to said first SOI wafer, said first SOI wafer providing a substrate for said second SOI wafer.

8. A method as in claim 7, further comprising the step of:

f) dicing stacked second SOI wafer and said first SOI wafer into individual three dimensional (3D) laminated chips.

9. A method of placing and wiring a circuit design, said method comprising the steps of:

a) receiving an integrated circuit design;

b) initially placing and wiring a majority of design circuit elements in a first circuit layer, buffers being placed on said first circuit layer after placing non-buffers;

c) conducting performance analysis on the placed and wired said first circuit layer;

d) selectively removing circuit elements placed on said first circuit layer including one or more said buffers;

e) placing remaining circuit elements and removed said circuit elements on a second circuit layer; and

f) wiring said second layer, elements on said second circuit layer being connected to corresponding elements on said first circuit layer.

10. A method as in claim 9, wherein said circuit elements remaining after the step (b) of initially placing and wiring are buffers for combinational logic on said first circuit layer.

11. A method as in claim 9, wherein the step (e) of placing said remaining circuit elements comprises selecting circuit elements from an array of circuit elements.

12. A method as in claim 11, wherein said array of circuit elements is an array of drivers.

13. A method of fabricating an integrated circuit (IC) chip, said method comprising:

providing an IC design;

placing and wiring said IC design comprising;

initially placing and wiring logic in said IC design on a single layer,

conducting performance analysis on the placed and wired said logic, and

placing and wiring buffers on a second circuit layer, buffers on said second circuit layer being wired to corresponding circuit elements on said single circuit layer;

fabricating the circuit layers;

attaching said second circuit layer to said single circuit layer; and

forming connection channels extending from circuit elements in said single circuit layer and in said second circuit layer, a three dimensional (3D) IC being formed by said circuit elements in said single circuit layer being connected to said buffers in said second circuit layer.