Semiconductor-based porous structure enabled by capillary force

• US 7,723,760 B2
• Filed: 10/31/2007
• Issued: 05/25/2010
• Est. Priority Date: 09/16/2005
• Status: Expired due to Fees

• Current Assignee: University of Cincinnati
• Original Assignee: University of Cincinnati
• Inventors: Medis, Praveen, Shuja, Ahmed, Parimi, Srinivas, Henderson, H. Thurman, Gerner, Frank M.
• Primary Examiner(s): Pham; Thanh V
• Application Number:
  US11/932,951
• Publication Number:
  US 20080115912A1
• Time in Patent Office: 937 Days
• Field of Search: 257/E31.013, 257/E21.151, 257/E21.565, 165/104.22, 165/274, 165/302
• US Class Current: 257/276
• CPC Class Codes: F28D 15/043 forming loops, e.g. capillary pumped loops
• CPC Class Codes: H01L 23/427 Cooling by change of state, e.g. use of heat pipes by liquefied gas H01L23/445
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: Y10S 165/218 Condensor adapted to cover opening at top of vapor generator
• CPC Class Codes: Y10T 29/49396 Condenser, evaporator or vaporizer making

Abstract

The present invention is a MEMS-based two-phase LHP (loop heat pipe) and CPL (capillary pumped loop) using semiconductor grade silicon and microlithographic/anisotrophic etching techniques to achieve a planar configuration. The principal working material is silicon (and compatible borosilicate glass where necessary), particularly compatible with the cooling needs for electronic and computer chips and package cooling. The microloop heat pipes (μLHP™) utilize cutting edge microfabrication techniques. The device has no pump or moving parts, and is capable of moving heat at high power densities, using revolutionary coherent porous silicon (CPS) wicks. The CPS wicks minimize packaging thermal mismatch stress and improves strength-to-weight ratio. Also burst-through pressures can be controlled as the diameter of the coherent pores can be controlled on a sub-micron scale. The two phase planar operation provides extremely low specific thermal resistance (20-60 w/cm²). The operation is dependent upon a unique micropatterened CPS wick which contains up to millions per square centimeter of stacked uniform micro-through-capillaries in semiconductor-grade silicon, which serve as the capillary “engine,” as opposed to the stochastic distribution of pores in the typical heat pipe wick. As with all heat pipes, cooling occurs by virtue of the extraction of heat by the latent heat of phase change of the operating fluid into vapor.

Claims

1. A semiconductor-based structure, the structure comprising:

a first set of porous regions of a capillary-force enabled liquid pump comprising a plurality of uniform through-holes along a vertical direction of the semiconductor structure between a first surface of the semiconductor structure and a second surface of the semiconductor;

wherein the plurality of uniform through-holes are substantially uniformly distributed in the first set of porous regions; and

wherein a through-hole of the plurality of through-holes has a substantially high length to diameter aspect ratio;

a second set of non-porous regions suitable for thermally conducting heat to the first set of porous regions at a first surface of the semiconductor structure.

2. The structure of claim 1, wherein the semiconductor-based structure is substantially comprised of, crystalline silicon.

3. The structure of claim 2, wherein the crystalline silicon is of the [100]-type.

4. The structure of claim 3, wherein the crystalline silicon is CMOS-grade n-type silicon.

5. A semiconductor-based monolithic evaporator structure, comprising:

a semiconductor substrate of the monolithic evaporator structure formed with,

a first vertical layer of pores having a first plurality of holes of a first diameter, a length of the first plurality of pores extending along a substantially vertical direction of the substrate;

a second vertical layer of rods formed from a second plurality of holes of a second diameter, a length of the second plurality of holes extending along the substantially vertical direction of the substrate, the second vertical layer of rods are formed vertically adjacent to a first end the first vertical layer of pores;

wherein the second diameter is greater than the first diameter such that a pre-determined number of rods of the second vertical layer of posts are physically coupled to a pore of the first vertical layer of pores at the first end; and

wherein the first vertical layer of pores and the second vertical layer of rods are substantially uniformly distributed in a region of a plane that is substantially normal to the vertical direction of the substrate.

6. The structure of claim 5, wherein the semiconductor substrate is further formed with at least one outlet coupled to one or more vapor channels formed by inherent presence of voids in the second vertical layer of rods.

7. The structure of claim 5, wherein the semiconductor substrate is formed with at least one inlet coupled to one or more of the first plurality of holes of a second end of the first vertical layer of pores.

8. The structure of claim 5, wherein the semiconductor-based structure is substantially comprised of, crystalline silicon.

9. The structure of claim 8, wherein the crystalline silicon is in the [100] direction.

10. The structure of claim 9, wherein the crystalline silicon is CMOS-grade n-type silicon.

11. The structure of claim 5, wherein a hole of the second plurality of holes has a substantially high length to diameter aspect ratio.

12. A semiconductor-based monolithic evaporator structure, comprising:

a semiconductor substrate of the monolithic evaporator structure having formed within it,

a first vertical layer of pores having a first plurality of holes of a first diameter, the length of the first plurality of pores extending along a substantially vertical direction of the substrate;

a second vertical layer of rods formed from a second plurality of holes of a second diameter, the length of the second plurality of holes extending along the substantially vertical direction of the substrate, the second vertical layer of rods are formed vertically adjacent to a first end the first vertical layer of pores;

a third vertical layer of pores having a third plurality of holes, the length of the third plurality of pores extending along a substantially vertical direction of the substrate, the third vertical layer of pores are formed vertically adjacent to a second end of the first vertical layer of pores;

wherein the second diameter is greater than the first diameter such that a pre-determined number of rods of the second vertical layer of posts are physically coupled to a pore of the first vertical layer of pores at the first end; and

wherein the first vertical layer of pores and the second vertical layer of rods are substantially uniformly distributed in a region of a plane that is substantially normal to the vertical direction of the substrate.

13. The structure of claim 12, wherein the semiconductor substrate is further formed with at least one outlet coupled to one or more vapor channels formed by inherent presence of voids in the second vertical layer of rods.

14. The structure of claim 12, wherein the semiconductor substrate is formed with at least one inlet coupled to the third layer of vertical pores.

15. The structure of claim 12, wherein the semiconductor-based structure is substantially comprised of, crystalline silicon.

16. The structure of claim 15, wherein the crystalline silicon is in the [100] direction.

17. The structure of claim 16, wherein the crystalline silicon is CMOS-grade n-type silicon.

18. The structure of claim 12, wherein a hole of the second plurality of holes has a substantially high length to diameter aspect ratio.