Trench structure semiconductor device and method for producing it

• US 7,723,782 B2
• Filed: 08/31/2006
• Issued: 05/25/2010
• Est. Priority Date: 08/31/2005
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Hirler, Franz
• Primary Examiner(s): Nguyen; Thinh T
• Application Number:
  US11/469,070
• Publication Number:
  US 20070126056A1
• Time in Patent Office: 1,363 Days
• Field of Search: 257330-332, 257/E29.066, 257/E29.183, 257/E29.198, 257/E29.327, 438/259, 438/270, 438/271, 438/589
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41 characterised by their shape, relative sizes or dispositions
• CPC Class Codes: H01L 29/732 Vertical transistors
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

A trench structure semiconductor device is disclosed. In one embodiment, field electrode devices are arranged in a trench structure, in direct spatial proximity in comparison with essentially planar or smooth conditions, have an enlarged common interface region with an insulation material in between, whereby a comparatively stronger electrical coupling of the directly adjacent field electrode devices is achieved.

Claims

1. A trench structure semiconductor device, comprising:

a semiconductor material region with a surface region;

at least one trench structure with a wall region and a bottom region, the at least one trench structure being provided in the interior of the semiconductor material region;

a plurality of field electrode devices formed in the interior of the trench structure as an electrode arrangement in a manner spaced apart and electrically insulated from one another and from the wall region of the trench structure by means of an insulation region; and

enlarged non-planar common interface regions with an insulation material between spatially directly adjacent and mutually adjoining field electrode devices, interfaces of the field electrode devices in the respective common interface regions being folded into one another with a mutually conformal course,

wherein the insulation material has an essentially homogenous thickness.

2. The trench structure semiconductor device as claimed in claim 1,in which the enlarged common interface region is formed by means of an increased roughness of at least one of the mutually opposite interfaces in the material of spatially directly adjacent and mutually adjoining field electrode devices in the interface region.

3. The trench structure semiconductor device as claimed in claim 2, in which the increased roughness is formed in the region of at least one of the field electrode devices, so that the insulation region has a homogeneous thickness, in particular.

4. The trench structure semiconductor device as claimed claim 1, in which the interface region is formed by means of one or a plurality of cutouts of at least one of the mutually opposite interfaces in the material of spatially directly adjacent and mutually adjoining field plate electrode devices in the interface region.

5. The trench structure semiconductor device as claimed in claim 1, in which the interface region is formed by means of one or a plurality of elevations of at least one of the mutually opposite interfaces in the material of spatially directly adjacent and mutually adjoining field plate electrode devices in the interface region.

6. The trench structure semiconductor device as claimed in claim 4, in which cutouts and/or elevations are in each case formed in the material of a field electrode device, so that the insulation has a homogeneous thickness, in particular.

7. The trench structure semiconductor device as claimed in claim 4, in which cutouts and/or elevations of one of the mutually opposite interfaces in the material of a first field electrode device in the interface region with a second, directly adjacent field electrode device adjoining the first are formed such that they cooperate or are in engagement in each case with corresponding elevations and/or cutouts of the directly adjacent and adjoining interface of the directly adjacent, adjoining and opposite interface in the material of the second field electrode device directly adjacent to and adjoining the first field electrode device in the interface region, so that the insulation has the essentially homogeneous thickness, in particular.

8. The trench structure semiconductor device as claimed in claim 4, in which—

viewed in cross section—

the mutually opposite interfaces of spatially directly adjacent and mutually adjoining field electrode devices are formed such that they cooperate or are intermeshed in comb-like fashion or in comb-shaped fashion.

9. The trench structure semiconductor device as claimed in claim 4, in which—

viewed in cross section—

the mutually opposite interfaces of spatially directly adjacent and mutually adjoining field electrode devices are formed such that they cooperate or are intermeshed in y-like fashion or in y-shaped fashion or in the form of a tuning fork.

10. The trench structure semiconductor device as claimed in claim 1, in which the trench structures are formed in a manner proceeding from the surface region of the semiconductor material region essentially in a first extension direction, which runs perpendicular to the surface region of the semiconductor material region, into the semiconductor material region.

11. The trench structure semiconductor device as claimed in claim 10, in which the field electrode devices of the electrode arrangement are formed as a stringing together of field electrode devices in the first extension direction in the interior of the trench structure.

12. The trench structure semiconductor device as claimed in claim 1, in which the trench structures are formed essentially in a second extension direction, which runs parallel to the surface region of the semiconductor material region, in the semiconductor material region.

13. The trench structure semiconductor device as claimed in claim 1, in which the field electrode device is formed in potential-free fashion or in floating fashion.

14. The trench structure semiconductor device as claimed in claim 1, in which a further electrode device, and in particular a control electrode device or a gate electrode device, is formed in the interior of the trench structure in a manner facing the surface region of the semiconductor material region and in a manner spatially separated and electrically insulated from the electrode arrangement of the plurality of field electrode devices by the insulation region and from the wall region of the trench structure, from the bottom region of the trench structure and/or from the semiconductor material region.

15. The trench structure semiconductor device as claimed in claim 14, in which the further electrode device is at a fixed electrical potential, in particular at source potential.

16. The trench structure semiconductor device as claimed in claim 1, which is formed as a device or as a combination of devices from the group consisting of a FET, a MOSFET, a trench transistor, a field plate transistor, a vertical transistor, a vertical trench transistor, an IGBT device, a p-channel transistor, a bipolar transistor, a diode device and a Schottky diode device.

17. The trench structure semiconductor device as claimed in claim 1, in which a pillar region doped oppositely to the doping of the surroundings is formed in the semiconductor material region and outside the trench structure and spatially at a distance from the latter, proceeding from the surface region of the semiconductor material region, the pillar region extending into the interior of the semiconductor material region.

18. The trench structure semiconductor device as claimed in claim 1, in which pairs of spatially directly adjacent field electrode devices which, in a common interface region, adjoin one another and are opposite one another are formed, relative to one another, in a targeted manner with differing degrees of pairwise electrical coupling or capacitance between the field electrode devices of the pairs of spatially directly adjacent field electrode devices which, in a common interface region, adjoin one another and are opposite one another, with respect to one another, in particular by means of a correspondingly targeted variation of the thickness of the insulation provided between the field electrode devices.

19. The trench structure semiconductor device as claimed in claim 1, in which the field electrode devices are formed such that they are electrically connected to one another via zener diodes or in high-impedance fashion in the trench structure or in an edge region.

20. A trench structure semiconductor device, comprising:

a semiconductor material region with a surface region;

means for providing at least one trench structure with a wall region and a bottom region, the at least one trench structure being provided in the interior of the semiconductor material region;

means for providing a plurality of field electrode devices formed in the interior of the trench structure means as an electrode arrangement in a manner spaced apart and electrically insulated from one another and from the wall region of the trench structure by an insulation region; and

enlarged non-planar common interface regions with an insulation material between spatially directly adjacent and mutually adjoining field electrode devices, interfaces of the field electrode devices in the respective common interface regions being folded into one another with a mutually conformal course,

wherein the insulation material has an essentially homogeneous thickness.