Semiconductor device and method for forming the same

• US 7,723,788 B2
• Filed: 02/11/2009
• Issued: 05/25/2010
• Est. Priority Date: 10/09/1992
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Teramoto, Satoshi, Takemura, Yasuhiko, Zhang, Hongyong
• Primary Examiner(s): COLEMAN, WILLIAM D
• Application Number:
  US12/369,578
• Publication Number:
  US 20090152631A1
• Time in Patent Office: 468 Days
• Field of Search: 257/347, 257/E27.111
• US Class Current: 257/347
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: Y10S 257/90 MOSFET type gate sidewall insulating spacer

Abstract

A thin film transistor device reduced substantially in resistance between the source and the drain by incorporating a silicide film, which is fabricated by a process comprising forming a gate insulator film and a gate contact on a silicon substrate, anodically oxidizing the gate contact, covering an exposed surface of the silicon semiconductor with a metal, and irradiating an intense light such as a laser beam to the metal film either from the upper side or from an insulator substrate side to allow the metal coating to react with silicon to obtain a silicide film. The metal silicide layer may be obtained otherwise by tightly adhering a metal coating to the exposed source and drain regions using an insulator formed into an approximately triangular shape, preferably 1 μm or less in width, and allowing the metal to react with silicon.

Claims

1. A semiconductor device comprising:

a thin film transistor comprising;

a semiconductor layer formed on an insulating surface;

a first impurity region and a second impurity region formed in the semiconductor layer;

a channel region formed between the first impurity region and the second impurity region;

a first metal silicide region formed on the first impurity region and a second metal silicide region formed on the second impurity region;

a gate electrode formed over the semiconductor layer with a gate insulating film interposed therebetween;

a first side wall and a second side wall adjacent to the gate electrode with a first insulating film interposed between the first side wall and the gate electrode;

a second insulating film formed over the gate electrode, the first insulating film, the first side wall and the second side wall; and

an electrode formed over the second insulating film and electrically connected to the first metal silicide region,

wherein the first metal silicide region is isolated from the insulating surface by the first impurity region and the second metal silicide region is isolated from the insulating surface by the second impurity region, and

wherein a maximum width of the first side wall in a channel direction is larger than a thickness of the first insulating film.

2. A semiconductor device according to claim 1, wherein the first insulating film comprises oxide of the gate electrode.

3. A semiconductor device according to claim 1, wherein the first insulating film comprises silicon oxide.

4. A semiconductor device according to claim 1, wherein the semiconductor layer has a thickness of 50 nm or less.

5. A semiconductor device according to claim 1, wherein the first metal silicide region and the second metal silicide region comprise at least one selected from molybdenum, tungsten, platinum, chromium, titanium, and cobalt.

6. A semiconductor device according to claim 1, wherein the first metal silicide region and the second metal silicide region comprises cobalt silicide.

7. A semiconductor device according to claim 1, wherein the first metal silicide region and the second metal silicide region comprise platinum silicide.

8. A semiconductor device according to claim 1, wherein each of the first impurity region and the second impurity region comprises two portions and one of the portions contains a lower concentration of impurities than the other portion, and is closer to the gate electrode than the other portion.

9. A semiconductor device according to claim 1, wherein the first insulating film and the third insulating film comprise oxide of the first gate electrode and oxide of the second gate electrode, respectively.

10. A semiconductor device according to claim 1, wherein a side surface of the semiconductor layer is coextensive with an edge of the first metal silicide region and another side surface of the semiconductor layer is coextensive with an edge of the second metal silicide region.

11. A semiconductor device comprising:

an N-type thin film transistor comprising;

a first semiconductor layer formed on an insulating surface;

a first impurity region and a second impurity region formed in the first semiconductor layer;

a first channel region formed between the first impurity region and the second impurity region;

a first metal silicide region formed on the first impurity region and a second metal silicide region formed on the second impurity region;

a first gate electrode formed over the first semiconductor layer with a first gate insulating film interposed therebetween;

a first side wall and a second side wall adjacent to the first gate electrode with a first insulating film interposed between the first side wall and the first gate electrode;

a second insulating film formed over the first gate electrode, the first insulating film, the first side wall and the second side wall; and

a first electrode formed over the second insulating film and electrically connected to the first metal silicide region, and

a P-type thin film transistor comprising;

a second semiconductor layer formed on the insulating surface;

a third impurity region and a fourth impurity region formed in the second semiconductor layer;

a second channel region formed between the third impurity region and the fourth impurity region;

a third metal silicide region formed on the third impurity region and a fourth metal silicide region formed on the fourth impurity region and;

a second gate electrode formed over the second semiconductor layer with a second gate insulating film interposed therebetween;

a third side wall and a fourth side wall adjacent to the second gate electrode with a third insulating film interposed between the third side wall and the second gate electrode;

a fourth insulating film formed over the second gate electrode, the third insulating film, the third side wall and the fourth side wall; and

a second electrode formed over the fourth insulating film and electrically connected to the third metal silicide region,

wherein the first metal silicide region is isolated from the insulating surface by the first impurity region, the second metal silicide region is isolated from the insulating surface by the second impurity region, the third metal silicide region is isolated from the insulating surface by the third impurity region and the fourth metal silicide region is isolated from the insulating surface by the fourth impurity region

wherein a maximum width of the third side wall in a second channel direction is larger than a thickness of the third insulating film.

12. A semiconductor device according to claim 11, wherein the first insulating film and the third insulating film comprise oxide of the first gate electrode and oxide of the second gate electrode, respectively.

13. A semiconductor device according to claim 11, wherein the first insulating film and third insulating film comprises silicon oxide.

14. A semiconductor device according to claim 11, wherein each of the first semiconductor layer and the second semiconductor layer has a thickness of 50 nm or less.

15. A semiconductor device according to claim 11, wherein the first metal silicide region, the second metal silicide region, the third metal silicide region and the fourth metal silicide region comprise cobalt silicide.

16. A semiconductor device according to claim 11, wherein the first metal silicide region, the second metal silicide region, the third metal silicide region and the fourth metal silicide region comprise platinum silicide.

17. A semiconductor device according to claim 11, wherein the first metal silicide region, the second metal silicide region, the third metal silicide region and the fourth metal silicide region comprise at least one selected from molybdenum, tungsten, platinum, chromium, titanium, and cobalt.

18. A semiconductor device according to claim 11, wherein each of the first impurity region, the second impurity region, the third impurity region and the fourth impurity region comprises two portions, and one of the portions contains a lower concentration of impurities than the other portion, and is closer to the first gate electrode than the other portion.

19. A semiconductor device according to claim 11, wherein a side surface of the first semiconductor layer is coextensive with an edge of the first metal silicide region, another side surface of the first semiconductor layer is coextensive with an edge of the second metal silicide region, a side surface of the second semiconductor layer is coextensive with an edge of the third metal silicide region and another side surface of the second semiconductor layer is coextensive with an edge of the fourth metal silicide region.

20. A semiconductor device comprising:

a thin film transistor comprising;

a semiconductor layer formed on an insulating surface;

a first impurity region and a second impurity region formed in the semiconductor layer;

a channel region formed between the first impurity region and the second impurity region;

a first metal silicide region formed on the first impurity region and a second metal silicide region formed on the second impurity region;

a gate electrode formed over the semiconductor layer with a gate insulating film interposed therebetween;

a first side wall and a second side wall adjacent to the gate electrode with a first insulating film interposed between the first side wall and the gate electrode;

a second insulating film formed over the gate electrode, the first insulating film, the first side wall and the second side wall; and

an electrode formed over the second insulating film and electrically connected to the first metal silicide region,

wherein the first impurity region overlaps with the first side wall and the second impurity region overlaps with the second side wall and,

wherein the first metal silicide region is isolated from the channel region by the first impurity region and the second metal silicide region is isolated from the channel region by the second impurity region, and

wherein a maximum width of the first side wall in a channel direction is larger than a thickness of the first insulating film.

21. A semiconductor device according to claim 20, wherein the first insulating film comprises oxide of the gate electrode.

22. A semiconductor device according to claim 20, wherein the first insulating film comprises silicon oxide.

23. A semiconductor device according to claim 20, wherein the semiconductor layer has a thickness of 50 nm or less.

24. A semiconductor device according to claim 20, wherein the first metal silicide region and the second metal silicide region comprise at least one selected from molybdenum, tungsten, platinum, chromium, titanium, and cobalt.

25. A semiconductor device according to claim 20, wherein the first metal silicide region and the second metal silicide region comprises cobalt silicide.

26. A semiconductor device according to claim 20, wherein the first metal silicide region and the second metal silicide region comprise platinum silicide.

27. A semiconductor device according to claim 20, wherein each of the first impurity region and the second impurity region comprises two portions and one of the portions contains a lower concentration of impurities than the other portion, and is closer to the gate electrode than the other portion.

28. A semiconductor device according to claim 20, wherein a side surface of the semiconductor layer is coextensive with an edge of the first metal silicide region and another side surface of the semiconductor layer is coextensive with an edge of the second metal silicide region.

29. A semiconductor device comprising:

an N-type thin film transistor comprising;

a first semiconductor layer formed on an insulating surface;

a first impurity region and a second impurity region formed in the first semiconductor layer;

a first channel region formed between the first impurity region and the second impurity region;

a first metal silicide region formed on the first impurity region and a second metal silicide region formed on the second impurity region;

a first gate electrode formed over the first semiconductor layer with a first gate insulating film interposed therebetween;

a first side wall and a second side wall adjacent to the first gate electrode with a first insulating film interposed between the first side wall and the first gate electrode;

a second insulating film formed over the first gate electrode, the first insulating film, the first side wall and the second side wall; and

a first electrode formed over the second insulating film and electrically connected to the first metal silicide region, and

a P-type thin film transistor comprising;

a second semiconductor layer formed on the insulating surface;

a third impurity region and a fourth impurity region formed in the second semiconductor layer;

a second channel region formed between the third impurity region and the fourth impurity region;

a third metal silicide region formed on the third impurity region and a fourth metal silicide region formed on the fourth impurity region and;

a second gate electrode formed over the second semiconductor layer with a second gate insulating film interposed therebetween;

a third side wall and a fourth side wall adjacent to the second gate electrode with a third insulating film interposed between the third side wall and the second gate electrode;

a fourth insulating film formed over the second gate electrode, the third insulating film, the third side wall and the fourth side wall; and

a second electrode formed over the fourth insulating film and electrically connected to the third metal silicide region,

wherein the first impurity region overlaps with the first side wall, the second impurity region overlaps with the second side wall, the third impurity region overlaps with the third side wall and the fourth impurity region overlaps with the fourth side wall,

wherein the first metal silicide region is isolated from the first channel region by the first impurity region, the second metal silicide region is isolated from the first channel region by the second impurity region, the third metal silicide region is isolated from the second channel region by the third impurity region and the fourth metal silicide region is isolated from the second channel region by the fourth impurity region,

wherein a maximum width of the third side wall in a second channel direction is larger than a thickness of the third insulating film.

30. A semiconductor device according to claim 29, wherein the first insulating film and third insulating film comprises silicon oxide.

31. A semiconductor device according to claim 29, wherein each of the first semiconductor layer and the second semiconductor layer has a thickness of 50 nm or less.

32. A semiconductor device according to claim 29, wherein the first metal silicide region, the second metal silicide region, the third metal silicide region and the fourth metal silicide region comprise cobalt silicide.

33. A semiconductor device according to claim 29, wherein the first metal silicide region, the second metal silicide region, the third metal silicide region and the fourth metal silicide region comprise platinum silicide.

34. A semiconductor device according to claim 29, wherein the first metal silicide region, the second metal silicide region, the third metal silicide region and the fourth metal silicide region comprise at least one selected from molybdenum, tungsten, platinum, chromium, titanium, and cobalt.

35. A semiconductor device according to claim 29, wherein each of the first impurity region, the second impurity region, the third impurity region and the fourth impurity region comprises two portions, and one of the portions contains a lower concentration of impurities than the other portion, and is closer to the first gate electrode than the other portion.

36. A semiconductor device according to claim 29, wherein a side surface of the first semiconductor layer is coextensive with an edge of the first metal silicide region, another side surface of the first semiconductor layer is coextensive with an edge of the second metal silicide region, a side surface of the second semiconductor layer is coextensive with an edge of the third metal silicide region and another side surface of the second semiconductor layer is coextensive with an edge of the fourth metal silicide region.

37. A semiconductor device comprising:

an N-type thin film transistor comprising;

a first semiconductor layer formed on an insulating surface;

a first impurity region and a second impurity region formed in the first semiconductor layer;

a first channel region formed between the first impurity region and the second impurity region;

a first metal silicide region formed on the first impurity region and a second metal silicide region formed on the second impurity region;

a first gate electrode formed over the first semiconductor layer with a first gate insulating film interposed therebetween;

a first side wall and a second side wall adjacent to the first gate electrode with a first insulating film interposed between the first side wall and the first gate electrode;

a second insulating film formed over the first gate electrode, the first insulating film, the first side wall and the second side wall; and

a first electrode formed over the second insulating film and electrically connected to the first metal silicide region, and

a P-type thin film transistor comprising;

a second semiconductor layer formed on the insulating surface;

a third impurity region and a fourth impurity region formed in the second semiconductor layer;

a second channel region formed between the third impurity region and the fourth impurity region;

a third metal silicide region formed on the third impurity region and a fourth metal silicide region formed on the fourth impurity region and;

a second gate electrode formed over the second semiconductor layer with a second gate insulating film interposed therebetween;

a third side wall and a fourth side wall adjacent to the second gate electrode with a third insulating film interposed between the third side wall and the second gate electrode;

a fourth insulating film formed over the second gate electrode, the third insulating film, the third side wall and the fourth side wall; and

a second electrode formed over the fourth insulating film and electrically connected to the third metal silicide region,

wherein the first metal silicide region, the second metal silicide region, the third silicide region and the fourth metal silicide region comprise same metal elements,

wherein a maximum width of the third side wall in a second channel direction is larger than a thickness of the third insulating film.

38. A semiconductor device according to claim 37, wherein the first insulating film and the third insulating film comprise oxide of the first gate electrode and oxide of the second gate electrode, respectively.

39. A semiconductor device according to claim 37, wherein the first insulating film and third insulating film comprises silicon oxide.

40. A semiconductor device according to claim 37, wherein each of the first semiconductor layer and the second semiconductor layer has a thickness of 50 nm or less.

41. A semiconductor device according to claim 37, wherein the first metal silicide region, the second metal silicide region, the third metal silicide region and the fourth metal silicide region comprise cobalt silicide.

42. A semiconductor device according to claim 37, wherein the first metal silicide region, the second metal silicide region, the third metal silicide region and the fourth metal silicide region comprise platinum silicide.

43. A semiconductor device according to claim 37, wherein the first metal silicide region, the second metal silicide region, the third metal silicide region and the fourth metal silicide region comprise at least one selected from molybdenum, tungsten, platinum, chromium, titanium, and cobalt.

44. A semiconductor device according to claim 37, wherein each of the first impurity region, the second impurity region, the third impurity region and the fourth impurity region comprises two portions, and one of the portions contains a lower concentration of impurities than the other portion, and is closer to the first gate electrode than the other portion.

45. A semiconductor device according to claim 37, wherein a side surface of the first semiconductor layer is coextensive with an edge of the first metal silicide region, another side surface of the first semiconductor layer is coextensive with an edge of the second metal silicide region, a side surface of the second semiconductor layer is coextensive with an edge of the third metal silicide region and another side surface of the second semiconductor layer is coextensive with an edge of the fourth metal silicide region.