Stacked semiconductor package and method of making same

• US 7,723,852 B1
• Filed: 01/21/2008
• Issued: 05/25/2010
• Est. Priority Date: 01/21/2008
• Status: Expired due to Fees

• Current Assignee: Amkor Technology Singapore Holding Pte., Ltd. (Amkor Technology Incorporated)
• Original Assignee: Amkor Technology Incorporated
• Inventors: Ha, Sung Chul, Kim, Bong Chan, Lee, Sung Min, Chung, Ji Young, Song, Jae Kyu, Kim, Do Hyung, Kim, Yoon Joo, Kim, In Tae
• Primary Examiner(s): CLARK, JASMINE JHIHAN B
• Application Number:
  US12/017,266
• Time in Patent Office: 855 Days
• Field of Search: 257/723, 257/777, 257/685, 257/686, 257/726, 257/783, 257/787, 257E25031-E25032, 257/E23.042, 257/E27.137, 257/E27.144, 438/6, 438/26, 438/66, 438/67, 438/107, 438/109, 438/406, 438455-459, 438FOR 211-FOR 220, 438/FOR.365, 438/FOR.366
• US Class Current: 257/777
• CPC Class Codes: H01L 2224/29101 the principal constituent melting at a temperature of less than 400°C
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48464 the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/73215 Layer and wire connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83101 as prepeg comprising a layer connector, e.g. provided in an insulating plate member
• CPC Class Codes: H01L 2224/83191 wherein the layer connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/838 Bonding techniques
• CPC Class Codes: H01L 2224/85447 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/92 Specific sequence of method steps
• CPC Class Codes: H01L 2224/92247 the second connecting process involving a wire connector
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06565 the devices having the same size and there being no auxiliary carrier between the devices
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/3135 : Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 24/27 : Manufacturing methods
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/33 : of a plurality of layer connectors
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

In accordance with the present invention, there is provided multiple embodiments of a semiconductor package including two or more semiconductor dies which are electrically connected to an underlying substrate through the use of conductive wires, some of which may be fully or partially encapsulated by an adhesive or insulating layer of the package. In a basic embodiment of the present invention, the semiconductor package comprises a substrate having a conductive pattern disposed thereon. Electrically connected to the conductive pattern of the substrate are first and second semiconductor dies. The first semiconductor die and a portion of the substrate are covered by an adhesive layer. The second semiconductor die, the adhesive layer and a portion of the substrate are in turn covered by a package body of the semiconductor package.

Claims

1. A semiconductor package, comprising:

a substrate having a conductive pattern disposed thereon;

a first semiconductor die electrically connected to the conductive pattern of the substrate;

a high flow layer applied to at least a portion of the first semiconductor die;

a low flow layer applied to at least a portion of the high flow layer;

a second semiconductor die attached to the low flow layer and electrically connected to the conductive pattern of the substrate; and

a package body at least partially encapsulating the first semiconductor die, the second semiconductor die, the high and low flow layers, and the substrate.

2. The semiconductor package of claim 1 wherein the substrate comprises:

an insulative layer defining opposed first and second surfaces;

a plurality of lands disposed on the first surface; and

a conductive pattern disposed on the second surface and electrically connected to the lands in a prescribed manner;

the first and second semiconductor dies each being electrically connected to the conductive pattern.

3. The semiconductor package of claim 2 wherein the first surface of the insulative layer and portions of each of the lands are covered by a solder mask.

4. The semiconductor package of claim 2 wherein the lands each include a solder ball electrically connected thereto.

5. The semiconductor package of claim 1 wherein the first semiconductor die is electrically connected to the conductive pattern through the use of first conductive wires.

6. The semiconductor package of claim 5 wherein the first conductive wires are each partially encapsulated by the high flow layer and partially encapsulated by the package body.

7. The semiconductor package of claim 1 wherein the second semiconductor die is electrically connected to the conductive pattern through the use of second conductive wires which are encapsulated by the package body.

8. The semiconductor package of claim 5 wherein the conductive pattern defines an inner region and an outer region, and the first conductive wires each extend to the inner region.

9. The semiconductor package of claim 8 wherein the second semiconductor die is electrically connected to the outer region of the conductive pattern through the use of second conductive wires which are encapsulated by the package body.

10. The semiconductor package of claim 9 wherein the first conductive wires are each partially encapsulated by the high flow layer and partially encapsulated by the package body.

11. The semiconductor package of claim 1 wherein the second semiconductor die is of a size approximately equal to that of the first semiconductor die.

12. The semiconductor package of claim 6 wherein the high flow layer is of a first viscosity, and the low flow layer is of a second viscosity differing from the first viscosity.

13. The semiconductor package of claim 12 wherein the first viscosity falls within the range of from about 5,000 poise to about 13,500 poise, and the second viscosity falls within the range of from about 13,500 poise to about 50,000 poise.

14. A method of fabricating a semiconductor package, comprising the steps of:

a) providing a substrate having a conductive pattern disposed thereon;

b) attaching a first semiconductor die to the substrate;

c) electrically connecting the first semiconductor die to the conductive pattern of the substrate;

d) encapsulating the first semiconductor die and covering at least a portion of the substrate with an adhesive layer which is attached to a second semiconductor die;

e) electrically connecting the second semiconductor die to the conductive pattern of the substrate; and

f) forming a package body to at least partially encapsulate the second semiconductor die, the adhesive layer and the substrate.

15. A semiconductor package, comprising:

a substrate comprising an insulative layer defining opposed first and second surfaces, a plurality of lands disposed on the first surface, and a conductive pattern disposed on the second surface and electrically connected to the lands in a prescribed manner;

a first semiconductor die electrically connected to the conductive pattern of the substrate;

a flow layer applied to a least a portion of the first semiconductor die;

a second semiconductor die attached to the flow layer and electrically connected to the conductive pattern of the substrate; and

a package body at least partially encapsulating the first semiconductor die, the second semiconductor die, the flow layer, and the substrate;

the flow layer including at least first and second portions which are of differing viscosities.

16. A semiconductor package, comprising:

a substrate having a conductive pattern disposed thereon;

a first semiconductor die electrically connected to the conductive pattern of the substrate through the use of first conductive wires;

a flow layer applied to a least a portion of the first semiconductor die;

a second semiconductor die attached to the flow layer and electrically connected to the conductive pattern of the substrate; and

a package body at least partially encapsulating the first semiconductor die, the second semiconductor die, the flow layer, and the substrate;

the flow layer including at least first and second portions, the first portion of the flow layer being of a first viscosity and the second portion of the flow layer being of a second viscosity which exceeds the first viscosity, the first conductive wires each being partially encapsulated by the first portion of the flow layer and partially encapsulated by the package body.

17. The semiconductor package of claim 16 wherein the second semiconductor die is electrically connected to the conductive pattern through the use of second conductive wires which are encapsulated by the package body.

18. The semiconductor package of claim 17, wherein:

the conductive pattern defines an inner region and an outer region;

the first conductive wires each extend to the inner region; and

the second conductive wires each extend to the outer region.