Leakage efficient anti-glitch filter

• US 7,724,025 B2
• Filed: 02/19/2008
• Issued: 05/25/2010
• Est. Priority Date: 06/08/2004
• Status: Expired due to Fees

• Current Assignee: Intellectual Ventures Funding LLC (Intellectual Ventures LLC)
• Original Assignee: Intellectual Ventures Funding LLC (Intellectual Ventures LLC)
• Inventors: Masleid, Robert
• Primary Examiner(s): Chang; Daniel D
• Application Number:
  US12/033,712
• Publication Number:
  US 20080143376A1
• Time in Patent Office: 826 Days
• Field of Search: 326/26, 326/27, 326/82, 326/83, 326/121, 327/34, 327/276
• US Class Current: 326/26
• CPC Class Codes: H03K 17/6872 using complementary field-effect transistors
• CPC Class Codes: H03K 19/00361 in field effect transistor circuits
• CPC Class Codes: H03K 5/1252 Suppression or limitation of noise or interference specially adapted for transmission systems H04B15/00, H04L25/08
• CPC Class Codes: H03K 5/133 using a chain of active delay devices

Abstract

A leakage efficient anti-glitch filter. In accordance with a first embodiment of the present invention, a leakage efficient anti-glitch filter with variable delay stages comprises a plurality of variable delay stages and a coincidence detector element for detecting coincidence of an input signal to the delay element and an output of the delay element. The plurality of variable delay stages may comprise stacked inverter circuits or stacked NAND circuits.

Claims

1. An anti-glitch filter circuit comprising:

a delay element comprising a stacked gate configured to produce a variable delay; and

a coincidence detector element configured to detect coincidence of an input signal to the delay element and an output signal of the delay element, wherein the coincidence detector element includes a glitch-filtered output signal output,

wherein said variable delay is configured for digital control.

2. The anti-glitch filter circuit of claim 1, wherein the glitch-filtered output signal output is configured such that spurious signals having a duration of less than a delay of the delay element are substantially eliminated.

3. The anti-glitch filter circuit of claim 2, wherein the coincidence detector element comprises a Mueller-C element.

4. The anti-glitch filter circuit of claim 2, wherein the stacked gate comprises a NAND gate.

5. The anti-glitch filter circuit of claim 1 wherein the stacked gate comprises a stacked NAND-gate circuit.

6. The anti-glitch filter circuit of claim 5 wherein the stacked NAND-gate circuit comprises at least two p-type devices and at least two n-type devices.

7. The anti-glitch filter circuit of claim 6 wherein the stacked NAND-gate circuit is configured to have a greater switching time duration than an inversion performed by an inverter comprising only four active devices.

8. The anti-glitch filter circuit of claim 6 wherein the stacked NAND-gate circuit is configured to have less leakage current than an inverter comprising only four active devices.

9. The anti-glitch filter circuit of claim 6, wherein the stacked NAND-gate circuit comprises:

a first plurality of devices of a first type coupled in series; and

a second plurality of devices of a second type coupled in series, wherein the second type is opposite to the first type;

wherein the first and the second pluralities of devices are coupled in series and include at least five active devices.

10. A method of delaying an electronic signal, the method comprising:

accessing an electronic signal;

producing a delayed version of the electronic signal through a digitally controlled variable delay stage; and

combining the electronic signal and the delayed version of the electronic signal to produce a substantially glitch-free delayed electronic signal, wherein the glitch-free delayed electronic signal transitions in response to a coincidence of the electronic signal and the delayed version of the electronic signal.

11. The method of claim 10, wherein said combining comprises filtering glitches characterized as having a duration of less than a delay of said delayed version of said electronic signal.

12. The method of claim 10, wherein said combining is performed using a Mueller-C element.

13. The method of claim 10, wherein said producing is performed using a plurality of inverters.

14. The method of claim 13, wherein the plurality of inverters comprise a stacked inverter circuit.

15. The method of claim 14, wherein the stacked inverter circuit comprises at least two p-type devices coupled in series with at least two n-type devices.

16. The method of claim 15, wherein the stacked inverter circuit has a greater switching time duration than an inversion performed by an inverter comprising only two active devices.

17. The method of claim 15, wherein the stacked inverter circuit has less leakage current than an inverter comprising only two active devices.

18. The method of claim 15, wherein the stacked inverter circuit comprises:

a first plurality of devices of a first type coupled in series; and

a second plurality of devices of a second type coupled in series, wherein the second type is opposite to the first type;

wherein the first and the second pluralities of devices are coupled in series and comprise at least five active devices.

19. An electronic circuit comprising:

a plurality of delay stages including a plurality of stacked inverters coupled in series, wherein each of the plurality of stacked inverters comprise;

at least two devices of a first type coupled in series, wherein the at least two devices of a first type are further coupled in series to at least two devices of a second type coupled in series;

wherein the second type is opposite to the first type;

a plurality of multiplexers corresponding to the plurality of delay stages and configured to select between a signal present at a desired delay stage and a signal propagating from beyond a delay stage corresponding to a multiplexer; and

a coincidence detector circuit including first and second devices of a first type coupled in series, wherein the first and second devices of a first type are further coupled in series to third and fourth devices of a second type coupled in series.

20. The electronic circuit of claim 19, wherein gates of each device of the plurality of stacked inverters are coupled together.