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System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits

  • US 7,724,589 B2
  • Filed: 07/31/2006
  • Issued: 05/25/2010
  • Est. Priority Date: 07/31/2006
  • Status: Active Grant
First Claim
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1. A sub-system, comprising:

  • a component in communication with a plurality of memory circuits and a system, the component operable to receive a signal from the system and communicate the signal to at least one of the memory circuits after a controlled delay;

    wherein the component is separate from the plurality of memory circuits;

    wherein the signal is associated with an operation including at least one of a write operation, a read operation, a refresh operation, a mode register write operation, a mode register read operation, an activate operation, and a precharge operation;

    wherein the controlled delay associated with the operation is variable;

    wherein the controlled delay is a function of the signal or a previous signal;

    wherein the controlled delay includes a cumulative delay associated with at least one control or address signal, and at least one data signal.

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