System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits
First Claim
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1. A sub-system, comprising:
- a component in communication with a plurality of memory circuits and a system, the component operable to receive a signal from the system and communicate the signal to at least one of the memory circuits after a controlled delay;
wherein the component is separate from the plurality of memory circuits;
wherein the signal is associated with an operation including at least one of a write operation, a read operation, a refresh operation, a mode register write operation, a mode register read operation, an activate operation, and a precharge operation;
wherein the controlled delay associated with the operation is variable;
wherein the controlled delay is a function of the signal or a previous signal;
wherein the controlled delay includes a cumulative delay associated with at least one control or address signal, and at least one data signal.
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Abstract
A system and method are provided for delaying a signal communicated from a system to a plurality of memory circuits. Included is a component in communication with a plurality of memory circuits and a system. Such component is operable to receive a signal from the system and communicate the signal to at least one of the memory circuits after a delay. In other embodiments, the component is operable to receive a signal from at least one of the memory circuits and communicate the signal to the system after a delay.
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Citations
23 Claims
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1. A sub-system, comprising:
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a component in communication with a plurality of memory circuits and a system, the component operable to receive a signal from the system and communicate the signal to at least one of the memory circuits after a controlled delay; wherein the component is separate from the plurality of memory circuits; wherein the signal is associated with an operation including at least one of a write operation, a read operation, a refresh operation, a mode register write operation, a mode register read operation, an activate operation, and a precharge operation; wherein the controlled delay associated with the operation is variable; wherein the controlled delay is a function of the signal or a previous signal; wherein the controlled delay includes a cumulative delay associated with at least one control or address signal, and at least one data signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 12, 13, 14, 18, 19, 20)
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10. A method, comprising:
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receiving a signal from a system; and communicating the signal to at least one of a plurality of memory circuits after a controlled delay, utilizing a component in communication with the plurality of memory circuits and the system; wherein the component is separate from the plurality of memory circuits; wherein the signal is associated with an operation including at least one of a write operation, a read operation, a refresh operation, a mode register write operation, a mode register read operation, an activate operation, and a precharge operation; wherein the controlled delay associated with the operation is variable; wherein the controlled delay is a function of the signal or a previous signal; wherein the controlled delay includes a cumulative delay associated with at least one control or address signal, and at least one data signal.
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11. A sub-system, comprising:
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a component in communication with a plurality of memory circuits and a system, the component operable to receive a signal from at least one of the memory circuits and communicate the signal to the system after a controlled delay; wherein the component is separate from the plurality of memory circuits; wherein the signal is associated with an operation including at least one of a write operation, a read operation, a refresh operation, a mode register write operation, a mode register read operation, an activate operation, and a precharge operation; wherein the controlled delay associated with the operation is variable; wherein the controlled delay is a function of the signal or a previous signal; wherein the controlled delay includes a cumulative delay associated with at least one control or address signal, and at least one data signal. - View Dependent Claims (15, 17, 21, 22, 23)
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16. A system, comprising:
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a component in communication with a plurality of memory circuits and the system, the component operable to receive a signal from at least one of the memory circuits and communicate the signal to the system after a controlled delay; wherein the component is separate from the plurality of memory circuits; wherein the signal is associated with an operation including at least one of a write operation, a read operation, a refresh operation, a mode register write operation, a mode register read operation, an activate operation, and a precharge operation; wherein the controlled delay associated with the operation is variable; wherein different delays are utilized in association with different signals; wherein the controlled delay includes a cumulative delay associated with at least one control or address signal, and at least one data signal.
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Specification