×

High speed bus with flow control and extended burst enhancements

  • US 7,724,669 B2
  • Filed: 08/09/2007
  • Issued: 05/25/2010
  • Est. Priority Date: 04/01/2003
  • Status: Active Grant
First Claim
Patent Images

1. In a networked system comprising a sender and a receiver interconnected by one or more buses, either or both the sender and receiver including or comprising one or more processors, a system for selectively varying the number of burst transfers used to transmit a block of data between the sender and receiver based on a size of a fractional portion of the block of data comprising:

  • computer memory containing first logic executed by said processor for transmitting the block of data from the sender to the receiver as n bursts, with the fractional portion forming one of the n bursts, if the size of any the fractional burst in the n bursts portion exceeds a threshold level, wherein n is an integer of two or more; and

    computer memory containing second logic executed by said processor for transmitting the block of data from the sender to the receiver as less than n bursts if the size of any the fractional burst in the n bursts portion is less than or equal to the threshold level, by extending at least one of the less than n bursts to include the fractional portion.

View all claims
  • 8 Assignments
Timeline View
Assignment View
    ×
    ×