High speed bus with flow control and extended burst enhancements
First Claim
1. In a networked system comprising a sender and a receiver interconnected by one or more buses, either or both the sender and receiver including or comprising one or more processors, a system for selectively varying the number of burst transfers used to transmit a block of data between the sender and receiver based on a size of a fractional portion of the block of data comprising:
- computer memory containing first logic executed by said processor for transmitting the block of data from the sender to the receiver as n bursts, with the fractional portion forming one of the n bursts, if the size of any the fractional burst in the n bursts portion exceeds a threshold level, wherein n is an integer of two or more; and
computer memory containing second logic executed by said processor for transmitting the block of data from the sender to the receiver as less than n bursts if the size of any the fractional burst in the n bursts portion is less than or equal to the threshold level, by extending at least one of the less than n bursts to include the fractional portion.
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Accused Products
Abstract
In a networked system, in which high speed busses interconnect sources and destinations of data, systems for and methods of flow control and extended burst transfers are described. The present invention is directed to a system for selectively varying the number of burst transfers used to transmit a block of data. The present invention is also directed to a method of selectively varying the number of burst transfers needed to transmit a block of data.
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Citations
9 Claims
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1. In a networked system comprising a sender and a receiver interconnected by one or more buses, either or both the sender and receiver including or comprising one or more processors, a system for selectively varying the number of burst transfers used to transmit a block of data between the sender and receiver based on a size of a fractional portion of the block of data comprising:
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computer memory containing first logic executed by said processor for transmitting the block of data from the sender to the receiver as n bursts, with the fractional portion forming one of the n bursts, if the size of any the fractional burst in the n bursts portion exceeds a threshold level, wherein n is an integer of two or more; and computer memory containing second logic executed by said processor for transmitting the block of data from the sender to the receiver as less than n bursts if the size of any the fractional burst in the n bursts portion is less than or equal to the threshold level, by extending at least one of the less than n bursts to include the fractional portion. - View Dependent Claims (2, 3, 4, 5)
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6. In a networked system, a method of selectively varying the number of burst transfers needed to transmit a block of data based on a size of a fractional portion of the block of data comprising the steps of:
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transmitting the block of data as n bursts, with the fractional portion forming one of the n bursts, if the size of the fractional portion exceeds a threshold level, wherein n is an integer of two or more; and transmitting the block of data as less than n bursts if the size of the fractional portion is less than or equal to the threshold level, by extending at least one of the less than n bursts to include the fractional portion. - View Dependent Claims (7, 8, 9)
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Specification