System and method for designing and implementing packet processing products
First Claim
1. A system for designing packet processing products, comprising:
- a user interface for allowing a user to define a desired packet processing algorithm using a plurality of discrete packet processing blocks, each of said blocks corresponding to a portion of said desired packet processing algorithm;
means for allowing the user to define connections between said plurality of packet processing blocks;
means for processing said plurality of packet processing blocks and said connections to provide a list of instructions in a hardware description language for producing an integrated circuit capable of executing said desired packet processing algorithm; and
a NETLIST generated using said list of instructions.
3 Assignments
0 Petitions
Accused Products
Abstract
A system and method for allowing a user to create instructions for building a packet processing integrated circuit. The system includes a user interface for allowing a user to define a desired packet processing algorithm (4) using a plurality of discrete packet processing blocks (22, 24, 28, 30), each of the blocks corresponding to a portion of the desired packet processing algorithm (4). The system allows the user to define connections (10) between the plurality of packet processing blocks (22, 24, 28, 30). The system processes a plurality of packet processing blocks (22, 24, 28, 30) and the connections to provide a list of instructions in a hardware description language for producing an integrated circuit capable of executing the desired packet processing algorithm (19). The list of instructions can be delivered to a customer (12), or the customer can receive an integrated circuit constructed using the list of instructions (19), or the customer can receive a NETLIST generated using said list of instructions (16). The plurality of packet processing blocks (22, 24, 28, 30) can include a Packet Processing Unit (PPU, PPUX) 22, a Packet Modification Unit (PMU) 28, and a Decision and Forwarding Unit (DFU) 30.
62 Citations
59 Claims
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1. A system for designing packet processing products, comprising:
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a user interface for allowing a user to define a desired packet processing algorithm using a plurality of discrete packet processing blocks, each of said blocks corresponding to a portion of said desired packet processing algorithm; means for allowing the user to define connections between said plurality of packet processing blocks; means for processing said plurality of packet processing blocks and said connections to provide a list of instructions in a hardware description language for producing an integrated circuit capable of executing said desired packet processing algorithm; and a NETLIST generated using said list of instructions. - View Dependent Claims (2)
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3. A system for designing packet processing products, comprising:
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a user interface for allowing a user to define a desired packet processing algorithm using a plurality of discrete packet processing blocks, each of said blocks corresponding to a portion of said desired packet processing algorithm; means for allowing the user to define connections between said plurality of packet processing blocks; and means for processing said plurality of packet processing blocks and said connections to provide a list of instructions in a hardware description language for producing an integrated circuit capable of executing said desired packet processing algorithm, wherein said plurality of packet processing blocks further includes a Packet Processing Unit (PPU) for; extracting a header of a packet; pointing to a portion of the header of a predetermined width using a predetermined index of a bit location in the header; comparing the data represented by the portion of the header with at least one predetermined value; and declaring a match when the result of the comparison is true. - View Dependent Claims (4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. A system for designing packet processing products, comprising:
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a user interface for allowing a user to define a desired packet processing algorithm using a plurality of discrete packet processing blocks, each of said blocks corresponding to a portion of said desired packet processing algorithm; means for allowing the user to define connections between said plurality of packet processing blocks; and means for processing said plurality of packet processing blocks and said connections to provide a list of instructions in a hardware description language for producing an integrated circuit capable of executing said desired packet processing algorithm, wherein said plurality of packet processing blocks further includes a Packet Modification Unit (PMU) for; extracting a packet; pointing to a portion of the packet of a predetermined width using a predetermined index of a bit location in the packet; and modifying the portion of the packet. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33)
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34. A system for designing packet processing products, comprising:
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a user interface for allowing a user to define a desired packet processing algorithm using a plurality of discrete packet processing blocks, each of said blocks corresponding to a portion of said desired packet processing algorithm; means for allowing the user to define connections between said plurality of packet processing blocks; and means for processing said plurality of packet processing blocks and said connections to provide a list of instructions in a hardware description language for producing an integrated circuit capable of executing said desired packet processing algorithm, wherein said plurality of packet processing blocks further includes a Decision and Forwarding Unit (DFU) for performing one of drop, queue, and forwarding operations on at least one packet. - View Dependent Claims (35, 36, 37, 38, 39, 40, 41, 42, 43, 44)
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45. A method for designing packet parsing and classification products, comprising the steps of:
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providing a user interface at a computer system for allowing a user to define a desired packet processing algorithm using a plurality of discrete packet processing blocks, each of said blocks corresponding to a portion of said desired packet processing algorithm; allowing the user to define connections between said plurality of packet processing blocks using said user interface of said computer system; processing said plurality of packet processing blocks and said connections to provide a list of instructions in a hardware description language for producing an integrated circuit capable of executing said desired packet processing algorithm; and generating a NETLIST using said list of instructions. - View Dependent Claims (46)
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47. A method for designing packet parsing and classification products, comprising the steps of:
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providing a user interface at a computer system for allowing a user to define a desired packet processing algorithm using a plurality of discrete packet processing blocks, each of said blocks corresponding to a portion of said desired packet processing algorithm; allowing the user to define connections between said plurality of packet processing blocks using said user interface of said computer system; processing said plurality of packet processing blocks and said connections to provide a list of instructions in a hardware description language for producing an integrated circuit capable of executing said desired packet processing algorithm; and filling out a connection document based on the plurality of packet processing blocks. - View Dependent Claims (48, 49, 50, 51)
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52. A method for designing packet parsing and classification products, comprising the steps of:
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providing a user interface at a computer system for allowing a user to define a desired packet processing algorithm using a plurality of discrete packet processing blocks, each of said blocks corresponding to a portion of said desired packet processing algorithm; allowing the user to define connections between said plurality of packet processing blocks using said user interface of said computer system; and processing said plurality of packet processing blocks and said connections to provide a list of instructions in a hardware description language for producing an integrated circuit capable of executing said desired packet processing algorithm, wherein the plurality of packet processing blocks includes a Packet Processing Unit (PPU) for; extracting a header of a packet; pointing to a portion of the header of a predetermined width using a predetermined index of a bit location in the header; comparing the data represented by the portion of the header with at least one predetermined value; and declaring a match when the result of the comparison is true. - View Dependent Claims (53, 54, 55)
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56. A system for designing packet processing products, comprising:
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a user interface for allowing a user to define a desired packet processing algorithm using a plurality of discrete packet processing blocks, each of said blocks corresponding to a portion of said desired packet processing algorithm; means for allowing the user to define connections between said plurality of packet processing blocks; means for processing said plurality of packet processing blocks and said connections to provide a list of instructions in a hardware description language for producing an integrated circuit capable of executing said desired packet processing algorithm; and a packet processing block for checksum or CRC generation or checking.
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57. A system for designing packet processing products, comprising:
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a user interface for allowing a user to define a desired packet processing algorithm using a plurality of discrete packet processing blocks, each of said blocks corresponding to a portion of said desired packet processing algorithm; means for allowing the user to define connections between said plurality of packet processing blocks; means for processing said plurality of packet processing blocks and said connections to provide a list of instructions in a hardware description language for producing an integrated circuit capable of executing said desired packet processing algorithm; and a packet processing block for packet header removal.
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58. A system for designing packet processing products, comprising:
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a user interface for allowing a user to define a desired packet processing algorithm using a plurality of discrete packet processing blocks, each of said blocks corresponding to a portion of said desired packet processing algorithm; means for allowing the user to define connections between said plurality of packet processing blocks; means for processing said plurality of packet processing blocks and said connections to provide a list of instructions in a hardware description language for producing an integrated circuit capable of executing said desired packet processing algorithm; and a packet processing block for packet header or trailer addition.
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59. A system for designing packet processing products, comprising:
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a user interface for allowing a user to define a desired packet processing algorithm using a plurality of discrete packet processing blocks, each of said blocks corresponding to a portion of said desired packet processing algorithm; means for allowing the user to define connections between said plurality of packet processing blocks; means for processing said plurality of packet processing blocks and said connections to provide a list of instructions in a hardware description language for producing an integrated circuit capable of executing said desired packet processing algorithm; and a packet processing block for per flow rate control.
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Specification