Clock adjustment for a handheld audio system

• US 7,724,843 B2
• Filed: 04/18/2006
• Issued: 05/25/2010
• Est. Priority Date: 04/18/2006
• Status: Expired due to Fees

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: SigmaTel Incorporated (NXP Semiconductors NV)
• Inventors: May, Michael R., Ragan, Lawrence Henry
• Primary Examiner(s): Payne, David C
• Assistant Examiner(s): Bolourchi, Nader
• Application Number:
  US11/405,887
• Publication Number:
  US 20070242780A1
• Time in Patent Office: 1,498 Days
• Field of Search: 375/340, 375/326
• US Class Current: 375/340
• CPC Class Codes: G11B 31/003 with radio receiver
• CPC Class Codes: H04B 1/0007 wherein the AD/DA conversion occurs at radiofrequency or intermediate frequency stage
• CPC Class Codes: H04B 1/1653 Detection of the presence of stereo signals and pilot signal regeneration
• CPC Class Codes: H04B 1/28 the receiver comprising at least one semiconductor device having three or more electrodes
• CPC Class Codes: H04B 1/30 for homodyne or synchrodyne receivers demodulator circuits H03D1/22
• CPC Class Codes: H04L 27/14 Demodulator circuits; Receiver circuits

Abstract

A handheld audio system having a radio signal decoder that includes a method for adjusting a system clock. Adjusting the system clock includes receiving a signal at a rate of a receive clock, wherein the signal includes data at a transmit rate. An error term is determined between the receive rate and the transmit rate. Based on the receive clock and the error term, where the error term is non-zero, a clock signal is generated.

Claims

1. A radio signal decoder comprising:

a front-end module operably coupled to, when enabled, convert a received radio signal into digital data in accordance with a rate of a receive clock, wherein the received radio signal includes data at a transmit rate; and

a baseband processing module operably coupled to process the digital data and to produce therefrom output digital data, wherein the baseband processing module includes;

a processing module; and

memory operably coupled to the processing module, wherein the memory stores operational instructions that cause the processing module to;

determine an error term between the rate of the receive clock and the transmit rate by;

recovering a pilot tone from the received signal;

generating a simulated pilot tone based on the receive clock;

mixing the simulated pilot tone with the recovered pilot tone to produce a mixed signal;

producing a difference of the simulated pilot tone and the recovered pilot tone based on the mixed signal; and

producing the error term based on the difference;

determine whether the error term is within an error tolerance; and

when the error term is not within the error tolerance, adjust the rate of the receive clock based on the error term to produce an adjusted receive clock rate.

2. A radio signal decoder comprising:

a front-end module configured to, when enabled, convert a received radio signal into digital data in accordance with a rate of a receive clock, wherein the received radio signal comprises a frequency modulated (“

FM”

) radio signal, which includes an embedded pilot tone that corresponds to the transmit rate and includes data transmitted at a transmit rate; and

a baseband processing module operably coupled to said front-end module, said baseband processing module configured to process the digital data and to produce therefrom output digital data, wherein the baseband processing module includes;

a processing module; and

memory operably coupled to the processing module, wherein the memory stores operational instructions that cause the processing module to;

determine an error term between the rate of the receive clock and the transmit rate;

determine whether the error term is within an error tolerance; and

when the error term is not within the error tolerance, adjust the rate of the receive clock based on the error term to produce an adjusted receive clock rate.

3. A radio signal decoder comprising:

a front-end module configured to, when enabled, convert a received radio signal into digital data in accordance with a rate of a receive clock, wherein the received radio signal includes data transmitted at a transmit rate; and

a baseband processing module operably coupled to said front-end module, said baseband processing module configured to process the digital data and to produce therefrom output digital data, wherein the baseband processing module includes;

a processing module; and

memory operably coupled to the processing module, wherein the memory stores operational instructions that cause the processing module to;

determine an error term between the receive rate and the transmit rate; and

generate a clock signal based on the receive clock and the error term, wherein the error term is non-zero by;

determining a fractional error of the receive clock based upon the error term; and

adjusting the clock signal based on the receive clock and the fractional error.

4. A radio signal decoder comprising:

a front-end module configured to, when enabled, convert a received radio signal into digital data in accordance with a rate of a receive clock, wherein the received radio signal includes data transmitted at a transmit rate; and

a baseband processing module operably coupled to said front-end module, said baseband processing module configured to process the digital data and to produce therefrom output digital data, wherein the baseband processing module includes;

a processing module; and

memory operably coupled to the processing module, wherein the memory stores operational instructions that cause the processing module to;

determine an error term between the receive rate and the transmit rate by;

recovering a pilot tone from the signal;

generating a simulated pilot tone based on the receive clock;

mixing the simulated pilot tone with the recovered pilot tone to produce a mixed signal;

producing a difference between the simulated pilot tone and the recovered pilot tone based on the mixed signal; and

producing the error term based on the difference; and

generate a clock signal based on the receive clock and the error term, wherein the error term is non-zero.

5. A radio signal decoder comprising:

a front-end module configured to, when enabled, convert a received radio signal into digital data in accordance with a rate of a receive clock, wherein the received radio signal comprises a frequency modulated (“

FM”

) radio signal, which includes an embedded pilot tone that corresponds to the transmit rate, and includes data transmitted at a transmit rate; and

a baseband processing module operably coupled to said front-end module, said baseband processing module configured to process the digital data and to produce therefrom output digital data, wherein the baseband processing module includes;

a processing module; and

memory operably coupled to the processing module, wherein the memory stores operational instructions that cause the processing module to;

determine an error term between the receive rate and the transmit rate; and

generate a clock signal based on the receive clock and the error term, wherein the error term is non-zero.