Execution optimization using a processor resource management policy saved in an association with an instruction group

• US 7,725,693 B2
• Filed: 09/22/2006
• Issued: 05/25/2010
• Est. Priority Date: 08/29/2005
• Status: Expired due to Fees

• Current Assignee: The Invention Science Fund I, L.L.C. (Intellectual Ventures LLC)
• Original Assignee: Searete LLC (Intellectual Ventures LLC)
• Inventors: Ferren, Bran, Myhrvold, Nathan P., Wood, JR., Lowell L., Hillis, W. Daniel, Tegreene, Clarence T.
• Primary Examiner(s): Chan, Eddie P
• Assistant Examiner(s): FAHERTY, COREY S
• Application Number:
  US11/526,190
• Publication Number:
  US 20070067611A1
• Time in Patent Office: 1,341 Days
• Field of Search: 712/23, 712/229
• US Class Current: 712/229
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 2209/507 Low-level
• CPC Class Codes: G06F 2212/6028 Prefetching based on hints or prefetch instructions
• CPC Class Codes: G06F 9/3844 using dynamic branch prediction, e.g. using branch history tables
• CPC Class Codes: G06F 9/3897 with adaptable data path
• CPC Class Codes: G06F 9/5011 the resources being hardware resources other than CPUs, Servers and Terminals
• CPC Class Codes: G06F 9/5016 the resource being the memory

Abstract

Embodiments include a device and a method. In an embodiment, a device provides a resource manager operable to select a resource management policy likely to provide a substantially optimum execution of an instruction group by comparing an execution of the instruction group pursuant to a first resource management policy applied to a hardware resource and an execution of the instruction group pursuant to a second resource management policy applied to the hardware resource.

Claims

1. A device comprising:

a processor;

a first and second hardware resource associated with the processor; and

a processor control unit operable to

fetch an instruction to be executed in the processor;

apply a first resource management policy to the first hardware resource, wherein the first resource management policy is;

(i) logically associated in a computer-readable medium with a first instruction group that includes the first instruction, and

(ii) selected based on at least one of theoretical information or historical information as likely to provide a substantially optimum execution of the first instruction group in response to a previous run-time execution of the first instruction group;

apply a second resource management policy to the second hardware resource, wherein the second resource management policy is;

(i) logically associated in a computer-readable medium with the first instruction group that includes the first instruction, and

(ii) selected based on at least one of theoretical information or historical information as likely to provide a substantially sub-optimum execution of the first instruction group in response to a previous run-time execution of the first instruction group such that greater than a preselected level of at least one error will occur during execution of the instruction group;

compare an execution of the first execution group pursuant to the first resource management policy with an execution of the first execution group pursuant to the second resource policy to determine an optimum resource management policy; and

apply the optimum resource management policy to the first hardware resource, wherein the first resource management policy and the second resource management policy can be selected as the optimum resource management policy based on the comparison.

2. The device of claim 1, wherein the processor control unit further comprises:

a processor control unit operable to enable the processor to execute the first instruction.

3. The device of claim 1, wherein the second hardware resource is of a similar type as the first hardware resource.

11. The device of claim 1, wherein the hardware resource includes a cache.

12. The device of claim 11, wherein the cache includes at least one of an on-chip cache or an off-chip cache.

13. The device of claim 1, wherein the hardware resource includes a branch predictor.

14. The device of claim 1, wherein the hardware resource includes a hardware resource logically associated with the processor.

15. The device of claim 1, wherein the hardware resource includes a hardware resource physically associated with the processor.

16. The device of claim 1, wherein the hardware resource associated with the processor includes a hardware resource managed by the processor.

17. The device of claim 16, wherein the hardware resource managed by the processor includes at least one of a memory, a bus, a register-file port, and a functional unit.

4. A method comprising:

fetching an instruction to be executed in a central processor unit having an associated resource;

receiving a previously selected resource management policy that is logically associated in a computer-readable medium with an instruction group that includes the instruction, the previously selected resource management policy having been selected in response to a comparison of a previous run-time execution of the instruction group pursuant to an optimistic resource policy selected as likely to based on at least one of theoretical information or historical information provide a substantially optimum execution of the instruction group, and a previous run-time execution of the instruction group pursuant to a pessimistic resource management policy selected as likely to based on at least one of theoretical information or historical information provide a substantially sub-optimum execution of the instruction group such that greater than a preselected level of at least one error will occur during execution of the instruction group;

applying the previously selected resource management policy to the resource, wherein the optimistic resource policy and the pessimistic resource management policy can be selected as the previously selected resource management policy based on the comparison; and

executing the instruction in the central processor unit.

5. The method of claim 4, wherein the fetching an instruction to be executed in a central processor unit having an associated resource includes fetching an instruction to be executed in a central processor unit having an associated cache resource.

6. The method of claim 5, wherein the associated cache resource includes one of an on-chip cache or an off-chip cache.

7. The method of claim 4, wherein the fetching an instruction to be executed in a central processor unit having an associated resource includes fetching an instruction to be executed in a central processor unit having an associated branch predictor resource.

8. The device of claim 4, wherein the processor and the hardware resource are formed on a single chip.

9. The device of claim 5, wherein the processor is formed on a first chip and the hardware resource is formed on a second chip.

10. The device of claim 4, wherein the processor control unit and the processor are formed on a single chip.

18. The method of claim 4, wherein the fetching an instruction to be executed in a central processor unit having an associated resource further includes:

fetching an instruction to be executed in a central processor unit having an associated resource, the associated resource including at least one of an associated resource implemented in hardware, software, and/or firmware.

19. The method of claim 4, wherein the fetching an instruction to be executed in a central processor unit having an associated resource further includes:

fetching an instruction to be executed in a central processor unit having an associated resource, the instruction including at least one of a functional instruction, a branching instruction, or a memory instruction.

20. The method of claim 4, wherein the fetching an instruction to be executed in a central processor unit having an associated resource further includes:

fetching an instruction to be executed in a central processor unit having an associated resource, the instruction including at least one of a statement or a portion of a statement.

21. The method of claim 4, wherein the fetching an instruction to be executed in a central processor unit having an associated resource further includes:

fetching an instruction to be executed in a central processor unit having an associated resource, the instruction including at least one of a translated instruction, and/or a micro-operation.

22. The method of claim 4, wherein the receiving a previously selected resource management policy associated with the instruction further includes:

fetching a previously selected resource management policy associated with the instruction.

23. A device comprising:

means for fetching an instruction to be executed in a central processor unit having an associated resource;

means for receiving a previously selected resource management policy logically associated in a computer-readable storage medium with the instruction, the resource management policy having been selected as likely to provide a substantially optimum execution of an instruction group that includes the instruction, and having been selected from a comparison between an execution of the instruction group pursuant to an optimistic resource management policy that assumes based on at least one of theoretical information or historical information that the instruction group will execute in a substantially optimal manner and an execution of the instruction group pursuant to a pessimistic resource management policy that assumes based on at least one of theoretical information or historical information that the instruction group will execute in a substantially sub-optimal manner such that greater than a preselected level of at least one error will occur during execution of the instruction group;

means for applying the previously selected resource management policy to the resource, wherein the optimistic resource management policy and the pessimistic resource management policy can be selected as the previously selected resource management policy based on the comparison; and

means for executing the instruction in the central processor unit.

24. A device comprising:

a processor;

a hardware resource associated with the processor; and

a processor control unit operable to

fetch an instruction;

fetch a resource management policy

(i) logically associated in a storage device with an instruction group that includes the instruction, and

(ii) having been selected from a comparison between an execution of the instruction group pursuant to an optimistic resource management policy that assumes based on at least one of theoretical information or historical information that the instruction group will execute in a substantially optimal manner and a pessimistic resource management policy that assumes based on at least one of theoretical information or historical information that the instruction group will execute in a substantially sub-optimal manner such that greater than a preselected level of at least one error will occur during execution of the instruction group;

apply the resource management policy to the hardware resource, wherein the optimistic resource management policy and the pessimistic resource management policy can be selected as the resource management policy based on the comparison; and

facilitate execution of the fetched instruction by the processor.

25. The device of claim 24, wherein the storage device includes a computer-readable medium.