Method and system for fast frequency switch for a power throttle in an integrated device
First Claim
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1. An apparatus comprising:
- a counter to count core clocks, the counter having a value to be incremented from zero to one less than a first bus ratio;
control logic to generate a control signal to change from the first bus ratio to a second bus ratio to change a frequency of the core clock, the control logic to receive the counter value and to control the counter based on the counter value.
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Abstract
In one embodiment, the present invention includes a counter to count core clocks, where the counter has a value to be incremented from zero to one less than a first bus ratio. Coupled to the counter may be a control logic to generate a control signal to change from the first bus ratio to a second bus ratio, where the control logic is coupled to receive the counter value and control the counter based on this value. In this way, the bus ratio can change without draining the transaction queues of a processor. Other embodiments are described and claimed.
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Citations
20 Claims
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1. An apparatus comprising:
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a counter to count core clocks, the counter having a value to be incremented from zero to one less than a first bus ratio; control logic to generate a control signal to change from the first bus ratio to a second bus ratio to change a frequency of the core clock, the control logic to receive the counter value and to control the counter based on the counter value. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A system comprising:
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a first processor including a pipeline having a plurality of pipe stages to generate a control signal to change from a first bus ratio to a second bus ratio, a core clock counter coupled to a first pipe stage of the plurality of pipe stages to count core clocks, the core clock counter having a value to be incremented from zero to one less than the first bus ratio, and control logic to receive a value of the core clock counter and to control the core clock counter based on the counter value; a system bus coupled to the first processor; a memory coupled to the system bus. - View Dependent Claims (11, 12, 13, 14)
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15. A method comprising:
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assigning a value of a core clock counter to an initial value if a reset is enabled; assigning the counter value to a current reload value if the counter value is zero, and assigning the counter value to an updated reload value if the counter value is zero and a switch signal is active, the switch signal indicative of a change in a core clock that is expected in a next bus clock cycle; generating a synchronization signal for a bus coupled to a processor when the counter value is zero. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification