Semiconductor integrated circuit and electronic device
First Claim
1. An electronic device including a motherboard mounted with a memory controller and a memory module interfaced to said memory controller, mounted with a plurality of memories and, comprising:
- a first dummy wiring which simulates and feeds back a path from said memory to a given characteristic impedance mismatching point present along a signal wiring reaching to said memory controller; and
a second dummy wiring which simulates and feeds back a path from said memory controller to a given characteristic impedance mismatching point present along a signal wiring reaching to said memory;
wherein said memory includes;
a first output circuit capable of variably setting signal transition time;
a first signal generating circuit which generates a test signal for the use in a setting operation of said signal transition time; and
a first controlling circuit which sets said signal transition time to said first output circuit based on a transmission delay time of said test signal which has been outputted from said first signal generating circuit to said first dummy wiring and fed back; and
said memory controller includes;
a second output circuit capable of variably setting signal transition time;
a second signal generating circuit which generates a test signal for setting said signal transition time; and
a second controlling circuit which sets said signal transition time to said second output circuit based on a transmission delay time of said test signal which has been outputted from said second signal generating circuit to said second dummy wiring and fed back.
5 Assignments
0 Petitions
Accused Products
Abstract
A dummy wiring 25 is provided for simulating an actual wiring 26 connecting semiconductor integrated circuits 2 and 6 on a circuit board. The semiconductor integrated circuit comprises a data output circuit 28 capable of variably setting the slew rate and a circuit 29 for measuring signal delay time between a signal sending point and a signal reflection point (characteristic impedance mismatching point) using the dummy wiring 25, and the delay time so obtained by the measuring circuit is used for the determination of the signal transition time of the output circuit. The transition time of the signal is set at least twice of the signal delay time between the signal sending point and the wiring branch at the nearest end. In this way, signal transmission with alleviated reflection by the reflection point at the nearest end is realized.
-
Citations
10 Claims
-
1. An electronic device including a motherboard mounted with a memory controller and a memory module interfaced to said memory controller, mounted with a plurality of memories and, comprising:
- a first dummy wiring which simulates and feeds back a path from said memory to a given characteristic impedance mismatching point present along a signal wiring reaching to said memory controller; and
a second dummy wiring which simulates and feeds back a path from said memory controller to a given characteristic impedance mismatching point present along a signal wiring reaching to said memory;
wherein said memory includes;
a first output circuit capable of variably setting signal transition time;
a first signal generating circuit which generates a test signal for the use in a setting operation of said signal transition time; and
a first controlling circuit which sets said signal transition time to said first output circuit based on a transmission delay time of said test signal which has been outputted from said first signal generating circuit to said first dummy wiring and fed back; and
said memory controller includes;
a second output circuit capable of variably setting signal transition time;
a second signal generating circuit which generates a test signal for setting said signal transition time; and
a second controlling circuit which sets said signal transition time to said second output circuit based on a transmission delay time of said test signal which has been outputted from said second signal generating circuit to said second dummy wiring and fed back.
- a first dummy wiring which simulates and feeds back a path from said memory to a given characteristic impedance mismatching point present along a signal wiring reaching to said memory controller; and
-
2. An electronic device according to claim 1 wherein said first output circuit outputs data strobe signals for the data read out from said memory, and said second output circuit outputs data strobe signals for the output of write data.
-
3. An electronic device including a motherboard mounted with a memory controller and a memory module mounted with a plurality of memories interfaced with said memory controller through a connector comprising:
- a first dummy wiring which simulates and feeds back a signal wiring path from said memory controller to said memory; and
a second dummy wiring which simulates and feeds back a signal wiring path from said memory controller to said connector along a signal wiring path from said memory to said memory controller;
wherein said memory includes;
a first output circuit capable of variably setting signal transition time; and
said memory controller includes;
a second output circuit capable of variably setting signal transition time;
a signal generating circuit which generates a test signal for the use in a setting operation of said signal transition time; and
a second controller which sets said signal transition time to said second output circuit based on a transmission delay time of the test signal which has been outputted from said signal generating circuit to said first dummy wiring and fed back; and
a first controller which determines said signal transition time of said first output circuit based on a difference in transmission time between said test signal which has been outputted from said signal generating circuit to said first dummy wiring and fed back and the test signal which has been outputted from said signal generating circuit to said second dummy wiring and fed back.
- a first dummy wiring which simulates and feeds back a signal wiring path from said memory controller to said memory; and
-
4. An electronic device including a motherboard mounted with a memory controller and a memory module interfaced to said memory controller, mounted with a plurality of memories, comprising:
-
a plurality of signal wirings connecting between the memory controller and the memories on the motherboard, wherein at least one of the signal wirings is a dummy wiring, the memory controller outputs a test signal to the dummy wiring for setting a signal transition time, and the memory controller sets the signal transition time based on a delay time of the test signal being fed back to the memory controller by the dummy wiring.
-
-
5. The electronic device according to claim 4, wherein the dummy wiring simulates a path from the memory controller to a given characteristic impedance mismatching point along one of the signal wirings and a feed back path from the impedance mismatching point to the memory controller.
-
6. The electronic device according to claim 4, wherein the memory controller comprises:
-
a signal generating circuit which generates the test signal; and a detection circuit for detecting the signal delay time, wherein the detection circuit detects a difference between a rise time of the test signal outputted from the signal generating circuit and a rise time of the test signal returned to the memory controller by the dummy wiring.
-
-
7. The electronic device according to claim 6, wherein the memory controller further comprises a slew rate setting register, a control code being set to the slew rate setting register corresponding to the detected time difference.
-
8. The electronic device according to claim 4, wherein the signal wirings comprises:
-
a first dummy wiring which simulates a path from the memory controller to the memory and a feed back path from the memory to the memory controller; and a second dummy wiring which simulates a path from the memory controller to a connector for mounting the memory module on the motherboard and a feed back path from the connector to the memory controller.
-
-
9. The electronic device according to claim 8, wherein the memory controller sets the signal transition time to a first output circuit included in the memory based on both the delay time of the test signal being fed back to the memory controller by the first dummy wiring and the delay time of the test signal being fed back to the memory controller by the second dummy wiring.
-
10. The electronic device according to claim 8, wherein the memory controller sets the signal transition time to a second output circuit included in the memory controller based on the delay time of the test signal being fed back to the memory controller by the first dummy wiring.
Specification