System and method for layout optimization using model-based verification

• US 7,725,845 B1
• Filed: 02/24/2007
• Issued: 05/25/2010
• Est. Priority Date: 02/24/2007
• Status: Expired due to Fees

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Nequist, Eric, White, David, Ruehl, Roland
• Primary Examiner(s): Chiang; Jack
• Assistant Examiner(s): BOWERS, BRANDON
• Application Number:
  US11/678,594
• Time in Patent Office: 1,186 Days
• Field of Search: 716/2
• US Class Current: 716/132
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: Y02P 90/02 Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

Method and system for chip optimization using model based verification (MBV) tool provide more accurate verification in determining hotspots and their characteristics. The MBV and the layout optimizer are implemented within a feedback loop. This type of verification allows for the MBV tool to provide hints, constraints and hotspot information to the layout optimizer. In addition, the model-based simulation results can be used to automatically fix the circuit designs and allow for specialized optimization flow for standard cell libraries.

Claims

1. A method for layout optimization comprising:

predicting a physical realization of a layout design based at least in part upon model parameters;

analyzing by a processor the predicted physical realization to determine hotspot optimization information, wherein the hotspot optimization information is associated at least in part with score and yield information of one or more hotspots;

providing the hotspot optimization information to a layout optimizer;

optimizing the layout design based at least in part upon the provided hotpot optimization information; and

storing the layout design in a volatile or non-volatile computer-usable medium or displaying the layout design on a display device.

2. The method of claim 1, further comprising providing hints and/or constraints.

3. The method of claim 1, further comprising automatically optimizing the layout design.

4. A method of claim 1, further comprising:

generating a database having models and hotspots information.

5. The method of claim 1, wherein the optimizing is based on pure model enabled geometry, computational electrical characteristics or post RC analysis.

6. The method of claim 1, wherein the optimizing is based on utilizing cost functions.

7. The method of claim 6, wherein the cost functions are based on rules, models, or a combination thereof.

8. The method of claim 1, wherein the layout design is part of standard cell libraries.

9. A system for layout optimization comprising:

means for predicting a physical realization of a layout design based at least in part upon model parameters;

a processor for analyzing the predicted physical realization to determine hotspot optimization information, wherein the hotspot optimization information is associated at least in part with score and yield information of one or more hotspots;

means for providing the hotspot optimization information to a layout optimizer;

means for optimizing the layout design based at least in part upon the provided hotpot optimization information; and

a volatile or non-volatile computer-usable medium for storing the layout design or a display device for displaying the layout design.

10. The system of claim 9, further comprising means for providing hints and/or constraints.

11. The system of claim 9, further comprising means for automatically optimizing the layout design.

12. The system of claim 9, wherein the means for optimizing is based on pure model enabled geometry, computational electrical characteristics or post RC analysis.

13. The system of claim 9, wherein the means for optimizing is based on utilizing cost functions.

14. The system of claim 9, wherein the layout design is part of standard cell libraries.

15. A computer program product embodied in a volatile or non-volatile computer-usable medium having executable code to execute a process by a processor for layout optimization, the process comprising:

predicting a physical realization of a layout design based at least in part upon model parameters;

analyzing the predicted physical realization to determine hotspot optimization information, wherein the hotspot optimization information is associated at least in part with score and yield information of one or more hotspots;

providing the hotspot optimization information to a layout optimizer;

optimizing the layout design based at least in part upon the provided hotpot optimization information; and

storing the layout design or displaying the layout design on a display device.

16. The product of claim 15, further comprising providing hints and/or constraints.

17. The product of claim 15, further comprising automatically optimizing the layout design.

18. The product of claim 15, wherein the optimizing is based on pure model enabled geometry, computational electrical characteristics or post RC analysis.

19. The product of claim 15, wherein the optimizing is based on utilizing cost functions.

20. The product of claim 15, wherein the layout design is part of standard cell libraries.