Method, storage media storing program, and component for avoiding increase in delay time in semiconductor circuit having plural wiring layers

• US 7,725,865 B2
• Filed: 09/28/2005
• Issued: 05/25/2010
• Est. Priority Date: 03/29/2005
• Status: Expired due to Fees

• Current Assignee: Socionext Inc.
• Original Assignee: Fujitsu Microelectronics Limited (Fujitsu Limited)
• Inventors: Oba, Hisayoshi
• Primary Examiner(s): ROSSOSHEK, YELENA
• Application Number:
  US11/236,532
• Publication Number:
  US 20060220255A1
• Time in Patent Office: 1,700 Days
• Field of Search: 716/1, 716/5, 716/7, 716/9, 716/12, 716/15, 438/18, 438/622, 257/48, 257/203, 257/74, 257/678, 257/686, 257/758, 257/773, 257/774
• US Class Current: 716/137
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method for a computer setting up a terminal layer of a semiconductor circuit having plural wiring layers including obtaining various kinds of information such as placement information relating to a plurality of cells or macros of the semiconductor circuit and being mounted onto a circuit board from a storage unit of the computer; comparing a driving capacity of a subject cell or macro, which is contained in the obtained information, and a resistance of wiring for connecting the subject cell or macro with the cell or macro at a connecting destination; and setting up a terminal layer based on a result of the comparing.

Claims

1. A terminal layer setting method, in the method for a computer setting up a terminal layer of a semiconductor circuit having a plurality of wiring layers, comprising:

obtaining by the computer various kinds of information such as placement information relating to a plurality of cells or macros constituting the semiconductor circuit and being mounted onto a circuit board from a storage unit of the computer;

comparing between a driver resistance of a subject cell or macro, which is contained in the obtained information, and a resistance of wiring for connecting the subject cell or macro with a cell or macro at a connecting destination by the computer;

setting up a terminal layer based on a result of the comparing by the computer; and

outputting a processing result of the setting up the terminal layer by the computer,

wherein the terminal layer is a wiring layer to which a wiring terminal is extended from the subject cell or macro for connecting the subject cell or macro with the cell or macro at the connecting destination.

2. The terminal layer setting method according to claim 1, wherein the wiring terminal of said cell or macro is extended to the wiring layer set up as an extending destination in a shortest path.

3. The terminal layer setting method according to claim 2, wherein extending the wiring terminal of the subject cell or macro to the wiring layer, which is set up as the extending destination, by adding a necessary number of terminal extending components, each including a Via and a wiring having a length thereof for adequately securing a contact with the Via, in the normal direction to a surface which the subject cell or macro is mounted onto.

4. The terminal layer setting method according to claim 1, wherein, if a wiring routing is required between said subject cell or macro and the cell or macro at the connecting destination of the subject cell or macro, the terminal layer is set up on a wiring layer which is set as said extending destination and on the neighboring wiring layer so as to make it possible to route wiring on the neighboring layer of a wiring layer that is specified as the extending destination.

5. The terminal layer setting method according to claim 1, wherein, if the driver resistance of the subject cell or macro is larger than a wiring resistance based on a distance between the subject cell or macro and the cell or macro at the connecting destination in said comparison, a wiring layer is set up for an extending destination of the wiring terminal of the subject cell or macro between wiring layers having a large wiring resistance per unit length of wiring.

6. The terminal layer setting method according to claim 1, wherein, if the driver resistance of the subject cell or macro is smaller than a wiring resistance based on a distance between the subject cell or macro and the cell or macro at the connecting destination in said comparison, a wiring layer is set up for an extending destination of the wiring terminal of the subject cell or macro between wiring layers having a small wiring resistance per unit length of wiring.

7. The terminal layer setting method according to claim 1, further comprising the steps of

judging whether or not the subject cell or macro is connected with a certain number, or greater, of cells or macros at connecting destinations;

and

setting up a wiring layer of the wiring terminal of the subject cell or macro at an extending destination between wiring layers having a small wiring capacitance per unit length of wiring, if the subject cell or macro is judged to be connected to more than or equal to the certain number of cells or macros at the connecting destinations.

8. The terminal layer setting method according to claim 1, further comprising the steps of

identifying an area on said board where wiring between said cells or macros and cells or macros at the connecting destination is congested based on obtained information;

and

setting up wiring layers for the cell or macro at an extending destination among a plurality of wiring layers in a distributed manner for the cells or macros included in the area where it is judged to be congested by wiring.

9. A storage media storing a terminal layer setting program, in the program for making a computer set up a terminal layer of a semiconductor circuit having a plurality of wiring layers, comprising:

obtaining various kinds of information such as placement information relating to a plurality of cells or macros constituting the semiconductor circuit and being mounted onto a circuit board from a storage unit of the computer;

comparing between a driver resistance of a subject cell or macro, which is contained in the obtained information, and a resistance of wiring for connecting the subject cell or macro with a cell or macro at a connecting destination; and

setting up a terminal layer based on a result of the comparing,

wherein the terminal layer is a wiring layer to which a wiring terminal is extended from the subject cell or macro for connecting the subject cell or macro with the cell or macro at the connecting destination.

10. The storage media storing the terminal layer setting program according to claim 9, wherein said program further comprising the step of designating to extend a wiring terminal of said plurality of cells or macros to a wiring layer set as an extending destination in the shortest path.

11. The storage media storing the terminal layer setting program according to claim 9, wherein said program further comprising the step of setting up the terminal layer on a wiring layer, which is set as said extending destination, and on the neighboring wiring layer so as to make it possible to route wiring on the neighboring layer of a wiring layer that is specified as the extending destination if a wiring routing is required between said subject cell or macro and the cell or macro at the connecting destination of the subject cell or macro.

12. The storage media storing the terminal layer setting program according to claim 9, wherein, if the driver resistance of the subject cell or macro is larger than a wiring resistance based on a distance between the subject cell or macro and the cell or macro at the connecting destination in said comparison step, a wiring layer is set up for an extending destination of the wiring terminal of the subject cell or macro between wiring layers having a large wiring resistance per unit length of wiring.

13. The storage media storing the terminal layer setting program according to claim 9, wherein, if the driver resistance of the subject cell or macro is smaller than a wiring resistance based on a distance between the subject cell or macro and the cell or macro at the connecting destination in said comparison, a wiring layer is set up for an extending destination of the wiring terminal of the subject cell or macro between wiring layers having a small wiring resistance per unit length of wiring.

14. The storage media storing the terminal layer setting program according to claim 9, further comprising the steps of

judging whether or not the subject cell or macro is connected with a certain number, or greater, of cells or macros at connecting destinations;

and

setting up a wiring layer of the wiring terminal of the subject cell or macro at an extending destination between wiring layers having a small wiring capacitance per unit length of wiring, if the subject cell or macro is judged to be connected to more than or equal to the certain number of cells or macros at the connecting destinations.

15. The storage media storing the terminal layer setting program according to claim 9, comprising the steps of

identifying an area on said board where wiring between said cells or macros and cells or macros at the connecting destination are congested based on obtained information;

and

setting up wiring layers for the cell or macro at an extending destination among a plurality of wiring layers in a distributed manner for the cells or macros included in the area where it is judged to be congested by wiring.