Testing a high speed serial bus within a printed circuit board

• US 7,727,004 B2
• Filed: 06/30/2006
• Issued: 06/01/2010
• Est. Priority Date: 06/30/2006
• Status: Expired due to Fees

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Pagano, Bill A., Spengler, David Louis
• Primary Examiner(s): Abrams; Neil
• Application Number:
  US11/480,087
• Publication Number:
  US 20080003884A1
• Time in Patent Office: 1,432 Days
• Field of Search: 439/482, 324/73.1, 324/72.5, 324/761, 324/754, 174/262, 174/266
• US Class Current: 439/482
• CPC Class Codes: H05K 1/0268 for electrical inspection or testing
• CPC Class Codes: H05K 2201/09627 Special connections between adjacent vias, not for grounding vias redundant conductors or connections H05K2201/0979
• CPC Class Codes: H05K 2201/1059 Connections made by press-fit insertion
• CPC Class Codes: H05K 2203/175 Configurations of connections suitable for easy deletion, e.g. modifiable circuits or temporary conductors for electroplating; Processes for deleting connections
• CPC Class Codes: H05K 3/306 Lead-in-hole components, e.g. affixing or retention before soldering, spacing means H05K3/32 takes precedence
• CPC Class Codes: H05K 3/42 Plated through-holes or plated via connections

Abstract

An apparatus and associated method for analyzing a communications link between two components on a common PCB. The communications link has a pair of through-board conductors connected by a first conductive etching on one side of the PCB. The communications link further has second etchings on an opposite side of the PCB respectively connecting each of the through-board conductors to one of the components. The first conductive etching can operably be open-circuited and connectors of an analyzer can be fitted to the through-board conductors to test the communications link between the components.

Claims

1. An apparatus comprising:

a printed circuit board (PCB) supporting a processor operably executing an operating system module;

an intelligent storage processor supported by the PCB;

a communications bus interconnecting the processors and having a pair of conductive vias that are not used to connect either of the processors to the PCB and that are sized to each operably engage one of a pair of probes that input data to a bus protocol analyzer, a first elongated trace extending entirely on one outer surface of the PCB interconnecting the conductive vias, and second elongated traces extending entirely on an opposite outer surface of the PCB respectively connecting each of the conductive vias to only one of the processors, the first elongated trace selectively openable to electrically isolate the two processors from each other with regard to storage communications.

2. The apparatus of claim 1 wherein the communications bus comprises a high speed serial bus.

3. The apparatus of claim 1 included in a distributed storage array.

4. The apparatus of claim 1 included in a controller passing access commands between a remote device and a storage space.

5. The apparatus of claim 4 wherein the access commands pass at a transfer rate of at least one gigabits per second.

6. An apparatus comprising:

a substrate;

a first processor attached to the substrate and a different second processor attached to the substrate; and

a serial communications link operably connecting the first and second processors, the serial communications link comprising;

a pair of through-substrate conductors;

a first elongated trace connecting the first processor to one of the through-substrate conductors;

a second elongated trace connecting the second processor to the other one of the through-substrate conductors; and

a third elongated trace on an external surface of the substrate connecting the pair of through-substrate conductors together, the third elongated trace selectively openable to electrically isolate the first and second processors from each other with regard to serial communications.

7. The apparatus of claim 6 wherein the first processor comprises a policy processor operably executing an operating system.

8. The apparatus of claim 7 wherein the second processor comprises an intelligent storage processor.

9. The apparatus of claim 6 included in a distributed storage array.

10. The apparatus of claim 6 included in a controller passing access commands between a remote device and a storage space.

11. The apparatus of claim 10 wherein the access commands pass at a transfer rate of at least one gigabits per second.

12. A printed circuit board assembly comprising a policy processor operably executing an operating system and connected via a serial communication bus to an intelligent storage processor, the serial communication bus including a link that is sized to selectively engage a bus protocol analyzer and that is selectively openable so that when the bus protocol analyzer is engaged all serial communications between the processors are communicated via the bus protocol analyzer.

13. The apparatus of claim 12 included in a distributed storage array.

14. The apparatus of claim 12 included in a controller passing access commands between a remote device and a storage space.

15. The apparatus of claim 14 wherein the access commands pass at a transfer rate of at least one gigabits per second.