Stacked die manufacturing process

• US 7,727,896 B1
• Filed: 11/06/2008
• Issued: 06/01/2010
• Est. Priority Date: 11/06/2008
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Rahman, Arifur
• Primary Examiner(s): Nhu; David
• Application Number:
  US12/266,194
• Time in Patent Office: 572 Days
• Field of Search: 438/106, 438/458, 438/637, 438/679, 438/692, 438/672, 438/700, 257/E21.17, 257/249, 257/304, 257/499, 257/511, 257/585
• US Class Current: 438/700
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0554 External layer
• CPC Class Codes: H01L 2224/0555 Shape
• CPC Class Codes: H01L 2224/0556 Disposition
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/157 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A method for forming a stacked-die structure is disclosed in which a buried oxide layer is formed in a semiconductor wafer. Device layers and metal layers are formed on the face side of the semiconductor wafer, defining dice, with each die including an interconnect region. Openings are etched in the interconnect regions that extend through the semiconductor wafer so as to expose portions of the buried oxide layer. Conductive material is deposited within the openings so as to form through-die vias. The semiconductor wafer is then attached to a wafer support structure and material is removed from the backside of the semiconductor wafer so as to form an oxide layer having a thickness that is less than the initial thickness of the buried oxide layer. Openings are then etched within the backside of the semiconductor wafer so as to expose the through-die vias, micro-bumps are deposited over the through-die vias, and stacked dice are attached to the micro-bumps so as to electrically couple the stacked dice to the through-die vias. Thereby, a stacked die structure is formed that includes an oxide layer on the backside of the base die. Since the method does not include any high temperature process steps after the semiconductor wafer has been attached to the wafer support structure, thermally-released double-sided tape or adhesive having a low thermal budget can be used to attach the semiconductor wafer to the wafer support structure.

Claims

1. A method for forming a stacked-die structure comprising:

forming a plurality of device layers on a face side of a semiconductor wafer that includes a buried oxide layer having a first thickness, the plurality of device layers defining a plurality of dice, each die including at least one interconnect region;

forming a plurality of metal layers over the plurality of device layers, the plurality of metal layers electrically coupled to the plurality of device layers;

etching openings in the interconnect regions that extend through the semiconductor wafer so as to expose portions of the buried oxide layer;

depositing conductive material within the openings so as to form through-die vias;

removing material from a backside of the semiconductor wafer so as to form an oxide layer having a second thickness that is less than the first thickness;

etching openings within the backside of the semiconductor wafer so as to expose the through-die vias; and

coupling a stacked die to the through-die vias.

2. The method for forming a stacked-die structure according to claim 1 further comprising:

attaching the face side of the semiconductor wafer to a wafer support structure using adhesive material such that the backside of the semiconductor wafer is exposed; and

wherein the removing material from the backside of the semiconductor wafer and the etching openings within the backside of the semiconductor wafer are performed while the face side of the semiconductor wafer is attached to the wafer support structure.

3. The method for forming a stacked-die structure according to claim 2 wherein the adhesive material has a thermal budget, and wherein the removing material from the backside of the semiconductor wafer, the etching openings within the backside of the semiconductor wafer and the coupling a stacked die to the through-die vias are all performed at a temperatures that do not exceed the thermal budget.

4. The method for forming a stacked-die structure according to claim 2 wherein the coupling a stacked die to the through-die vias further comprises:

depositing a plurality of micro-bumps such that each of the plurality of micro-bumps extends over one of the through-die vias;

placing a stacked die on the plurality of micro-bumps; and

heating the plurality of micro-bumps so as to electrically couple the stacked die to the through-die vias.

5. The method for forming a stacked-die structure according to claim 2 wherein the removing material from the backside of the semiconductor wafer further comprises:

performing a grinding process on the backside of the semiconductor wafer; and

performing a polishing process on the backside of the semiconductor wafer, the grinding process and the polishing process removing those portions of the semiconductor wafer that extend between the buried oxide layer and the backside of the semiconductor wafer and removing a portion of the buried oxide layer as to form the oxide layer.

6. The method for forming a stacked-die structure according to claim 2 wherein the etching openings in the interconnect regions further comprises performing a selective etch process, the selective etch process stopping on the buried oxide layer.

7. The method for forming a stacked-die structure according to claim 6 wherein the through-die vias are formed using a via-first process in which the buried oxide layer is formed prior to the forming a plurality of device layers and the etching openings in the interconnect regions is performed prior to the forming a plurality of metal layers.

8. The method for forming a stacked-die structure according to claim 2 further comprising forming at least one additional metal layer on the face side of the semiconductor wafer that is electrically coupled to the through-die vias and the plurality of device layers, the additional metal layer formed after the depositing conductive material within the openings so as to form through-die vias and before the removing material from the backside of the semiconductor wafer.

9. A method for forming a stacked-die structure comprising:

forming a semiconductor wafer that includes a buried oxide layer having a first thickness;

forming a plurality of device layers on a face side of the semiconductor wafer, the plurality of device layers defining a plurality of dice, each die including devices and at least one interconnect region;

forming a plurality of metal layers over the plurality of device layers, the plurality of metal layers electrically coupled to the plurality of device layers;

etching openings in the interconnect regions using a selective etch process, the selective etch process stopping on the buried oxide layer;

depositing conductive material within the openings so as to form through-die vias;

attaching the semiconductor wafer to a wafer support structure such that the backside of the semiconductor wafer is exposed;

removing material from the backside of the semiconductor wafer so as to form an oxide layer having a second thickness that is less than the first thickness;

etching openings within the backside of the semiconductor wafer so as to expose the through-die vias;

depositing a plurality of micro-bumps such that each of the plurality of micro-bumps extends over one of the through-die vias;

placing a plurality of stacked die on the plurality of micro-bumps; and

heating the plurality of micro-bumps so as to electrically couple the stacked die to the through-die vias.

10. The method for forming a stacked-die structure according to claim 9 wherein the removing material from the backside of the semiconductor wafer, the etching openings within the backside of the semiconductor wafer, the depositing a plurality of micro-bumps, the placing a plurality of stacked die on the plurality of micro-bumps and the heating are performed while the semiconductor wafer is attached to the wafer support structure.

11. The method for forming a stacked-die structure according to claim 10 wherein the attaching the semiconductor wafer to a wafer support structure further comprises attaching the face side of the semiconductor wafer to a wafer support structure using adhesive material having a thermal budget, and wherein none of the steps of removing material from the backside of the semiconductor wafer, etching openings within the backside of the semiconductor wafer, depositing a plurality of micro-bumps, the placing a plurality of stacked die on the plurality of micro-bumps and the heating are performed at temperatures that do not exceed the thermal budget.

12. The method for forming a stacked-die structure according to claim 11 wherein the adhesive material is thermally-released double-sided tape.

13. The method for forming a stacked-die structure according to claim 11 wherein the adhesive material comprises a layer of liquid adhesive.

14. The method for forming a stacked-die structure according to claim 13 wherein the removing material from the backside of the semiconductor wafer further comprises:

performing a grinding process on the backside of the semiconductor wafer; and

performing a polishing process on the backside of the semiconductor wafer, the grinding process and the polishing process removing those portions of the semiconductor wafer that extend between the buried oxide layer and the backside of the semiconductor wafer and removing a portion of the buried oxide layer as to form the oxide layer.

15. The method for forming a stacked-die structure according to claim 14 wherein the forming a plurality of device layers form field programmable gate array device die.

16. The method for forming a stacked-die structure according to claim 15 wherein the through-die vias are formed using a via-last process in which the buried oxide layer is formed prior to the forming a plurality of device layers, the forming a plurality of device layers is performed prior to the forming a plurality of metal layers, and further wherein the forming a plurality of metal layers is performed prior to the etching openings in the interconnect regions, the method further comprising:

forming at least one additional metal layer on the face side of the semiconductor wafer that is electrically coupled to the through-die vias and the plurality of device layers, the additional metal layer formed after the depositing conductive material within the openings so as to form through-die vias and before the removing material from the backside of the semiconductor wafer.

17. A method for forming a stacked-die structure comprising:

forming a plurality of device layers on a face side of a semiconductor wafer that includes a buried oxide layer having a first thickness, the plurality of device layers defining a plurality of dice, each die including devices and at least one interconnect region;

forming a plurality of metal layers over the plurality of device layers, the plurality of metal layers electrically coupled to the plurality of device layers;

etching openings in the interconnect regions that extend through the metal layers, the plurality of device layers and through the semiconductor wafer so as to expose portions of the buried oxide layer;

depositing conductive material within the openings so as to form through-die vias;

forming at least one additional metal layer on the face side of the semiconductor wafer that is electrically coupled to the through-die vias and the devices such that each die region forms a field programmable gate array die having a routing fabric and at least one interface tile that is coupled to the routing fabric, the interconnect region disposed within an interface tile;

attaching the semiconductor wafer to a wafer support structure using adhesive material having a thermal budget;

removing material from the backside of the semiconductor wafer so as to form an oxide layer having a second thickness that is less than the first thickness; and

etching openings within the backside of the semiconductor wafer so as to expose the through-die vias.

18. The method for forming a stacked-die structure according to claim 17 further comprising coupling a stacked die to the through-die vias.

19. The method for forming a stacked-die structure according to claim 17 wherein the removing material from the backside of the semiconductor wafer, the etching openings within the backside of the semiconductor wafer, and the coupling a stacked die to the through-die vias are performed while the semiconductor wafer is attached to the wafer support structure and are performed at a temperature that does not exceed a thermal budget.

20. The method for forming a stacked-die structure according to claim 18 further comprising;

forming metal interconnects on the oxide layer, the metal interconnects electrically coupled to some of the through-die vias; and

forming metal to silicon capacitors on the backside of the semiconductor wafer, the metal to silicon capacitors electrically coupled to the metal interconnects.