Small-pitch three-dimensional mask-programmable memory

• US 7,728,391 B2
• Filed: 11/06/2007
• Issued: 06/01/2010
• Est. Priority Date: 04/04/2004
• Status: Expired due to Fees

• Current Assignee: Guobiao Zhang
• Original Assignee: Guobiao Zhang
• Inventors: Zhang, Guobiao
• Primary Examiner(s): Pham; Long
• Application Number:
  US11/936,069
• Publication Number:
  US 20080054372A1
• Time in Patent Office: 938 Days
• Field of Search: 257/390, 257/401
• US Class Current: 257/390
• CPC Class Codes: G06F 21/10 Protecting distributed programs or content, e.g. vending or licensing of copyrighted material protection in video systems or pay television H04N7/16 ; Digital rights management [DRM]
• CPC Class Codes: G06F 21/62 Protecting access to data via a platform, e.g. using keys or access control rules
• CPC Class Codes: G06F 21/78 to assure secure storage of data address-based protection against unauthorised use of memory G06F12/14; record carriers for use with machines and with at least a part designed to carry digital markings G06K19/00
• CPC Class Codes: G11C 17/06 using diode elements G11C17/14 takes precedence
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices
• CPC Class Codes: H10B 20/20 Programmable ROM [PROM] devices comprising field-effect components H10B20/10 takes precedence

Abstract

The present invention discloses a small-pitch three-dimensional mask-programmable memory (SP-3DmM). It is an ultra-low-cost and ultra-high-density semiconductor memory. SP-3DmM comprises a mask-programmable memory level stacked above the substrate. This memory level comprises diodes but no transistors or antifuses. Its minimum line pitch is smaller than the minimum gate pitch of the substrate transistors.

Claims

1. A small-pitch three-dimensional mask-programmable memory (SP-3DmM), comprising:

a semiconductor substrate having a peripheral circuit, said peripheral circuit comprising a plurality of functional transistors, said functional transistors comprising a plurality of gates in parallel; and

at least one mask-programmable memory level stacked above said substrate and coupled to said peripheral circuit through a plurality of inter-level vias, said mask-programmable memory level comprising a plurality of diodes and a plurality of address-selection lines in parallel, said diodes coupled to said address-selection lines, whereby said peripheral circuit reads data from said mask-programmable memory level;

wherein the minimum pitch of said address-selection lines of said mask-programmable memory level is smaller than the minimum pitch of said gates of said functional transistors.

2. The SP-3DmM according to claim 1, wherein said mask-programmable memory level comprises no functional transistor.

3. The SP-3DmM according to claim 1, wherein said mask-programmable memory level requires no electrical programming.

4. The SP-3DmM according to claim 1, wherein said mask-programmable memory level comprises no antifuse.

5. The SP-3DmM according to claim 1, wherein:

said substrate further comprises a transistor-based memory, said transistor-based memory comprising a plurality of gates in parallel;

wherein the minimum pitch of said address-selection lines of said mask-programmable memory level is smaller than the minimum pitch of said gates of said transistor-based memory.

6. The SP-3DmM according to claim 5, wherein said transistor-based memory comprises an embedded RAM.

7. The SP-3DmM according to claim 5, wherein said transistor-based memory comprises an embedded ROM.

8. The SP-3DmM according to claim 1, wherein said diodes are natural-junction diodes.

9. The SP-3DmM according to claim 1, wherein said diodes are pillar-shaped diodes.

10. The SP-3DmM according to claim 1, wherein said diodes are junction diodes.

11. The SP-3DmM according to claim 10, wherein said junction diodes are p-n junction diodes.

12. The SP-3DmM according to claim 10, wherein said junction diodes are p-i-n junction diodes.

13. The SP-3DmM according to claim 1 wherein said diodes are Schottky diodes.

14. The SP-3DmM according to claim 1, further comprising at least two mask-programmable memory levels stacked above said substrate and coupled to said peripheral circuit.

15. The SP-3DmM according to claim 14, wherein adjacent mask-programmable memory levels share a level of address-selection lines.

16. The SP-3DmM according to claim 14, wherein adjacent mask-programmable memory levels are separated by an inter-level dielectric.

17. The SP-3DmM according to claim 1, wherein the minimum via pitch of said inter-level vias is larger than the minimum line pitch of said mask-programmable memory level.

18. The SP-3DmM according to claim 17, wherein selected ones of said inter-level vias are interleaved with respect to each other.

19. The SP-3DmM according to claim 17, wherein selected ones of said inter-level vias are displaced with respect to each other.