Semiconductor device, wiring substrate, and method for manufacturing wiring substrate

• US 7,728,439 B2
• Filed: 11/21/2003
• Issued: 06/01/2010
• Est. Priority Date: 11/21/2002
• Status: Active Grant

• Current Assignee: Godo Kaisha IP Bridge 1 (IP Bridge, Inc.)
• Original Assignee: NEC Corporation
• Inventors: Nishiyama, Tomohiro, Tago, Masamoto
• Primary Examiner(s): Purvis; Sue
• Assistant Examiner(s): Harrison; Monica D
• Application Number:
  US10/536,025
• Publication Number:
  US 20060151870A1
• Time in Patent Office: 2,384 Days
• Field of Search: 438/118, 438/15, 438/108, 257/778, 257/691, 257/E21.503, 257/E21.511
• US Class Current: 257/778
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12044 OLED
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/18161 of a flip chip

Abstract

The reliabilities of a wiring substrate and a semiconductor apparatus are improved by reducing the internal stress caused by the difference of thermal expansion coefficients between a base substrate and a semiconductor chip. A wiring layer (5) is provided on one surface of a silicon base (3). An electrode as the uppermost layer of the wiring layer (5) is provided with an external bonding bump (7). A through-electrode (4) is formed in the base (3) for electrically connecting the wiring layer (5) and an electrode terminal. The electrode terminal on the chip mounting surface is bonded to an electrode terminal of a semiconductor chip (1) by an internal bonding bump (6). The thermal expansion coefficient of the silicon base (3) is equivalent to that of the semiconductor chip (1) and not more than that of the wiring layer (5).

Claims

1. A semiconductor apparatus in which a semiconductor chip is mounted on a wiring substrate with Flip-Chip,

wherein the wiring substrate comprises:

a monolithic base substrate formed from any one of a silicon, a ceramic, or a photosensitive glass;

a wiring layer having an insulating layer and a wiring formed on a wiring layer formation surface which is one surface of the monolithic base substrate;

an electrode formed on a chip mounting surface which is a backside of the wiring layer formation surface of the monolithic base substrate; and

a through-electrode formed on the monolithic base substrate electrically connecting the wiring layer formed on the wiring layer formation surface and the electrode formed on the chip mounting surface,

wherein a thermal expansion coefficient of the monolithic base substrate is equal to a thermal expansion coefficient of the semiconductor chip, and the thermal expansion coefficient of the monolithic base substrate is less than a thermal expansion coefficient of the wiring layer,

wherein the semiconductor chip is bonded to the chip mounting surface with face-down.

2. The semiconductor apparatus according to claim 1, wherein a reinforcing frame is stuck at least on a part of an outer part of a chip mounting position of the chip mounting surface.

3. The semiconductor apparatus according to claim 2, wherein a thermal expansion coefficient of the reinforcing frame is equal to the thermal expansion coefficient of the semiconductor chip, or less than the thermal expansion coefficient of the wiring layer.

4. The semiconductor apparatus according to claim 1, wherein a thickness of the monolithic base substrate, at least a part of an outer part of a semiconductor chip mounting position at the chip mounting surface, is thicker than the semiconductor chip mounting position at the chip mounting surface.

5. The semiconductor apparatus according to claim 1, wherein a functional element is formed on at least any one of the wiring layer formation surface or the wiring layer.

6. The semiconductor apparatus according to claim 1, wherein the thermal expansion coefficient of the semiconductor chip is smaller than a thermal expansion coefficient of the wiring layer.

7. A wiring substrate which mounts a semiconductor chip with Flip-Chip,

wherein the wiring substrate comprises:

a monolithic base substrate formed from any one of a silicon, a ceramic, or a photosensitive glass;

a wiring layer having an insulating layer and a wiring formed on a wiring layer formation surface which is one surface of the monolithic base substrate;

an electrode formed on a chip mounting surface which is a backside of the wiring layer formation surface of the monolithic base substrate; and

a through-electrode formed on the monolithic base substrate electrically connecting the wiring layer formed on the wiring layer formation surface and the electrode formed on the chip mounting surface,

wherein a thermal expansion coefficient of the monolithic base substrate is equal to a thermal expansion coefficient of the semiconductor chip, and the thermal expansion coefficient of the monolithic base substrate is less than a thermal expansion coefficient of the wiring layer.

8. The wiring substrate according to claim 7, wherein a reinforcing frame is stuck at least on a part of an outer part of a chip mounting position of the chip mounting surface.

9. The wiring substrate according to claim 8, wherein a thermal expansion coefficient of the reinforcing frame is equal to the thermal expansion coefficient of the semiconductor chip, or less than the thermal expansion coefficient of the wiring layer.

10. The wiring substrate according to claim 7, wherein a thickness of the monolithic base substrate, at least a part of an outer part of a semiconductor chip mounting position at the chip mounting surface, is thicker than the semiconductor chip mounting position at the chip mounting surface.

11. The wiring substrate according to claim 7, wherein a functional element is formed on at least any one of the wiring layer formation surface or the wiring layer.

12. The wiring substrate according to claim 7, wherein the thermal expansion coefficient of the semiconductor chip is smaller than a thermal expansion coefficient of the wiring layer.

13. A method for manufacturing a wiring substrate which comprises a monolithic base substrate formed from any one of a silicon, a ceramic, or a photosensitive glass and a wiring layer having an insulating layer and a wiring formed on a wiring layer formation surface, which is one surface of the monolithic base substrate, and mounts a semiconductor chip with Flip-Chip, and a thermal expansion coefficient of the monolithic base substrate is equal to a thermal expansion coefficient of the semiconductor chip, and the thermal expansion coefficient of the monolithic base substrate is less than a thermal expansion coefficient of the wiring layer, the method comprising steps of:

forming a half-through-hole from the wiring layer formation surface of the monolithic base substrate;

forming a first electrode on the wiring layer formation surface by burying the half-through-hole with an electrically conductive material;

forming the wiring layer on the wiring layer formation surface; and

forming a second electrode for mounting the semiconductor chip by exposing the half-through-hole through thinning the monolithic base substrate from a backside of the wiring layer formation surface.

14. The method for manufacturing a wiring substrate according to claim 13, further comprising a step of:

thinning the monolithic base substrate by maintaining a step between at least one part of an outer part of a semiconductor chip mounting position and the other part of the semiconductor chip mounting position, by making a work amount smaller at least at the one part of the outer part of the semiconductor chip mounting position than the other part of the semiconductor chip mounting position.

15. The method for manufacturing a wiring substrate according to claim 13, further comprising a step of:

forming a functional element during forming the wiring layer.

16. A method for manufacturing a wiring substrate which comprises a monolithic base substrate formed from any one of a silicon, a ceramic, or a photosensitive glass and a wiring layer formed on a wiring layer formation surface, which is one surface of the monolithic base substrate, and mounts a semiconductor chip with Flip-Chip, and a thermal expansion coefficient of the monolithic base substrate is equal to a thermal expansion coefficient of the semiconductor chip, and the thermal expansion coefficient of the monolithic base substrate is less than a thermal expansion coefficient of the wiring layer, the method comprising steps of:

forming the wiring layer on the wiring layer formation surface of the monolithic base substrate;

forming a through-hole which penetrates only the monolithic base substrate from a backside of the wiring layer formation surface of the monolithic base substrate; and

forming an electrode for mounting the semiconductor chip at the backside of the wiring layer formation surface by burying the through-hole with an electrically conductive material.

17. The method for manufacturing a wiring substrate according to claim 16, further comprising a step of:

thinning the monolithic base substrate by maintaining a step between at least one part of an outer part of a semiconductor chip mounting position and an other part of the semiconductor chip mounting position, by making a work amount smaller at least at the one part of the outer part of the semiconductor chip mounting position than the other part of the semiconductor chip mounting position.

18. The method for manufacturing a wiring substrate according to claim 16, further comprising a step of:

forming a functional element during forming the wiring layer.