Non-invasive load current sensing in low dropout (LDO) regulators

• US 7,728,565 B2
• Filed: 11/12/2007
• Issued: 06/01/2010
• Est. Priority Date: 11/12/2007
• Status: Expired due to Fees

• Current Assignee: Exelis Incorporated (L3Harris Technologies, Inc.)
• Original Assignee: ITT Manufacturing Enterprises, Inc. (ITT, Inc.)
• Inventors: Wyatt, Michael A.
• Primary Examiner(s): Laxton; Gary L
• Application Number:
  US11/938,354
• Publication Number:
  US 20090121694A1
• Time in Patent Office: 932 Days
• Field of Search: 323/268, 323/269, 323/273, 323/277, 323/279, 323/316
• US Class Current: 323/269
• CPC Class Codes: G05F 1/46 wherein the variable actually regulated by the final control device is dc G05F1/625 takes precedence
• CPC Class Codes: G05F 1/56 using semiconductor devices in series with the load as final control devices G05F1/461 takes precedence

Abstract

A low dropout (LDO) voltage regulator includes an output terminal for providing a regulated voltage output to a load, and a plurality of PFETs connected in parallel. Each PFET drains a level of current and the sum of the levels of current are provided as a current output at the output terminal. The LDO voltage regulator also includes a feedback network coupled to the output terminal for providing a voltage feedback signal, and an error amplifier coupled between the plurality of PFETs and the feedback network for sensing a differential voltage. The error amplifier includes an output voltage which is provided to the plurality of PFETs for adjusting the drain of current from each PFET. A summation of the drains of current from each PFET is provided as the current output to regulate the voltage output at the output terminal. Each PFET drains a current level of I_0/n and the summation of the drains of current is the current output I₀.

Claims

1. An LDO voltage regulator comprising:

an output terminal for providing a regulated voltage output to a load,

a plurality of PFETs connected in parallel, wherein each PFET drains a level of current and the sum of the levels of current are provided as a current output at the output terminal, and

all drains of the plurality of PFETs are directly tied together to provide the regulated voltage output to the load,

a sensing network, including a sensing PFET, connected to the plurality of PFETs for sensing the level of current drained by each of the plurality of PFETs, wherein the sensing PFET includes a drain, which is not tied to the drains of the plurality of PFETs, and

an error amplifier coupled between the output terminal and the sensing network for providing a voltage to the sensing network,

wherein a summation of the drains of current from each PFET is provided as the current output to regulate the voltage output at the output terminal, and

the sensing network senses the level of current drained by each PFET of the plurality of PFETs, and provides the sensed level of current as an output control signal.

2. The LDO voltage regulator of claim 1 wherein

the plurality of PFETs include n PFETs, n being an integer greater than 1.

3. The LDO voltage regulator of claim 2 wherein

each of the n PFETs includes a source connected to a primary voltage, a gate connected to all other gates of the n PFETs, and a drain connected to the output terminal.

4. The LDO voltage regulator of claim 2 wherein

each PFET drains a current level of I₀/n and the summation of the drains of current is I₀.

5. The LDO voltage regulator of claim 2 wherein

the sensing PFET is separate from the plurality of PFETs, and the sensing PFET provides the same level of current as each PFET of the plurality of PFETs.

6. The LDO voltage regulator of claim 5 wherein

the sensing PFET includes a gate connected to all the gates of the PFETs of the plurality of PFETs, a source connected to a primary voltage and a drain connected to an inverting input terminal of an error amplifier.

7. The LDO voltage regulator of claim 6 wherein

a non-inverting input terminal of the error amplifier is connected to the output terminal.

8. The LDO voltage regulator of claim 6 wherein

the sensing network includes a cascode PFET having a gate connected to an output terminal of the error amplifier, a source connected to the drain of the sensing PFET, and a drain providing the sensed level of current as the output control signal.

9. The LDO voltage regulator of claim 8 wherein

the inverting input terminal of the error amplifier and the drain of the sensing PFET include a voltage level approximately corresponding to the regulated voltage output, and

the sensed level of current is approximately a level of current which is the same as a level of current in the drain of each PFET of the plurality of PFETs.

10. The LDO voltage regulator of claim 2 wherein

the output current level is I₀ and the drain of each PFET of the plurality of PFETs has a current level of I₀/n, and the sensed level of current is approximately I₀/n.

11. The LDO voltage regulator of claim 2 wherein

the sensing network is free-of resistor networks.

12. The LDO voltage regulator of claim 2 wherein

the regulated voltage output is provided to digital circuit elements in an integrated circuit, a system on a chip (SOC), or a circuit board.