Debug network for a configurable IC

• US 7,728,617 B2
• Filed: 09/22/2008
• Issued: 06/01/2010
• Est. Priority Date: 07/15/2005
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Tabula Incorporated
• Inventors: Redgrave, Jason, Khubchandani, Teju
• Primary Examiner(s): Tran, Anh Q
• Application Number:
  US12/235,581
• Publication Number:
  US 20090079468A1
• Time in Patent Office: 617 Days
• Field of Search: None
• US Class Current: 326/16
• CPC Class Codes: H03K 19/1731 Optimisation thereof
• CPC Class Codes: H03K 19/177 arranged in matrix form
• CPC Class Codes: H03K 19/17704 the logic functions being realised by the interconnection of rows and columns
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17748 Structural details of configuration resources
• CPC Class Codes: H03K 19/17756 for partial configuration or partial reconfiguration
• CPC Class Codes: H03K 19/17764 for reliability

Abstract

Some embodiments of the invention provide a configurable integrated circuit (IC) that includes several configurable circuits grouped in several tiles. The configurable IC also includes a configuration network for loading configuration data into the IC, where the configuration data is for configuring several of the configurable circuit. In some embodiments, the configuration network includes several registers at several boundaries between the tiles, where the registers allow multiple configuration data sets to be routed to multiple tiles concurrently. The configuration network in some embodiments includes several address counters at several tiles, where each address counter allows one address to be loaded for a tile and then to be successively incremented based on increment instructions sent over the configuration network. At least, two different addresses specified by an address counter of a particular tile identify two different resources within the particular tile.

Claims

1. An integrated circuit (“

IC”

) comprising;

a) a plurality of groups of configurable circuits arranged in rows and columns; and

b) a debug network for routing signals to said groups, said debug network comprising;

1) a plurality of lines arranged in a plurality of rows and columns that traverse the groups; and

2) a column select circuit for each column, wherein a particular column select circuit for a particular column is for receiving a signal and identifying whether the signal is directed to a group in the particular column.

2. The IC of claim 1, wherein signals are input on the plurality of lines on a same side of the IC as signals are output on the plurality of lines from the IC.

3. The IC of claim 2, wherein at least a sub-set of the plurality of lines are looped back through the IC in order to output signals from the sub-set of the plurality of lines on the same side of the IC as signals are input to the sub-set of the plurality of lines.

4. The IC of claim 1, wherein the debug network is separate from a data routing network for routing data between the groups.

5. The IC of claim 4, wherein the plurality of groups of configurable circuits include a plurality of configurable routing circuits that form said data routing network.

6. The IC of claim 1 further comprising a plurality of tiles, wherein the debug network further comprises a row selection circuit for each particular tile for identifying whether signals that are traversing down a column associated with the particular tile are addressed to the particular tile.

7. The IC of claim 1 further comprising a plurality of user design state (“

UDS”

) elements associated with each group for storing and outputting user design state values, said debug network for reading a plurality of user design values stored in a plurality of UDS elements.

8. An integrated circuit (“

IC”

) comprising;

a) a plurality of groups of configurable circuits; and

b) a debug network for routing data from the groups out of the IC, said debug network comprising;

i) a plurality of lines traversing the groups; and

ii) a plurality of registers between the groups for allowing one or more of said groups to concurrently output data.

9. The IC of claim 8, wherein said debug network is further for supplying a load address instruction to the plurality of groups.

10. The IC of claim 9, wherein said load address instruction identifies one or more resources within one or more of said groups, wherein two different load address instructions comprising two different addresses identify two different resources within a particular group.

11. The IC of claim 9, wherein each group comprises a plurality of circuits comprising said configurable circuits, wherein said debug network comprises a plurality of address counters at each of said groups, said address counter for storing an address that identifies one or more circuits within a group that is associated with said address counter and for successively incrementing said stored address upon receiving an increment address instruction.

12. The IC of claim 8, wherein each group comprises a plurality of circuits comprising said configurable circuits, wherein said debug network is further for routing an address that identifies a particular group and subsequently routing an address that identifies a set of circuits within said particular group, wherein said set of circuits is for outputting data to one of said registers upon being identified.

13. The IC of claim 12, wherein the set of circuits comprises a plurality of user design state (“

UDS”

) elements for storing and outputting user design state values.

14. The IC of claim 8, wherein the plurality of groups are arranged in rows and columns, wherein a first group is in a first row and a first column and a second group is in a second row and a second column, said first row different from said second row, said first column different from said second column, and wherein the registers are for allowing a particular data set to be routed to the first and second groups concurrently.

15. An integrated circuit (“

IC”

) comprising;

a) a plurality of groups of circuits comprising a plurality of configurable circuits for configurably performing operations; and

b) a debug network for collecting debug data from a plurality of said configurable circuits, said debug data comprising user data,

said debug network comprising a plurality of address counters at a plurality of the groups, wherein at least two different addresses specified by an address counter of a particular group identify two different circuits within the particular group.

16. The IC of claim 15, wherein said user data does not comprise configuration data.

17. The IC of claim 15, wherein said user data comprises output of a plurality of configurable circuits.

18. The IC of claim 15, wherein each address counter is for allowing one address to be loaded for a group and then to be successively incremented based on increment instructions sent over the debug network.

19. The IC of claim 15, wherein a load address instruction is sent over the debug network to load an address into an address counter of a particular group.

20. The IC of claim 19, wherein the address of the particular group is sent over the debug network before the load address instruction is sent over the debug network for the particular group.

21. The IC of claim 15, wherein said debug network is further for routing said collected debug data out of the IC.