Leakage current cancellation for integrated analog switch

• US 7,728,649 B1
• Filed: 10/30/2008
• Issued: 06/01/2010
• Est. Priority Date: 11/01/2007
• Status: Active Grant

• Current Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Original Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Inventors: Croft, Gregg D., Webb, Robert W.
• Primary Examiner(s): Nguyen; Hai L
• Application Number:
  US12/261,087
• Time in Patent Office: 579 Days
• Field of Search: 327/379, 327/403, 327/404, 327/427, 327/534, 327/535, 327/537
• US Class Current: 327/534
• CPC Class Codes: H03K 17/165 by feedback from the output circuit to the control circuit
• CPC Class Codes: H03K 2217/0036 Means reducing energy consumption

Abstract

An integrated analog switch including first and second semiconductor devices and a current mirror. The first device is a switching device having first and second current terminals coupled between first and second switch terminals. When turned off, the body of the first device is pulled to a bias voltage, and a first leakage current flows between its body and the first switch terminal. The second device is a reduced-size replica of the first device having one current terminal coupled to the first switch terminal and having its body pulled to about the bias voltage when turned off. The second device provides a second leakage current which is proportional to the leakage current of the first device. The current mirror circuit mirrors and amplifies the second leakage current to provide a cancellation current which is applied to the first switch terminal to cancel leakage current.

Claims

1. An integrated analog switch, comprising:

a first semiconductor device having first and second current terminals, a control terminal and a body, wherein said first and second current terminals are coupled to first and second switch terminals, respectively;

wherein said first semiconductor device, when turned off, causes a first leakage current between said body of said first semiconductor device and said first switch terminal;

a second semiconductor device comprising first and second current terminals, a control terminal and a body, wherein said first current terminal of said second semiconductor device is coupled to said first switch terminal and wherein said second current terminal of said second semiconductor device is coupled to said body of said first semiconductor device;

wherein said second semiconductor device, when turned off, causes a second leakage current between said body of said second semiconductor device and said first switch terminal, wherein said second leakage current is proportional to said first leakage current; and

a first current mirror circuit, coupled to said first switch terminal and to said body of said second semiconductor device, which mirrors and amplifies said second leakage current to provide a first cancellation current which is applied to said first switch terminal, wherein said first cancellation current is equivalent to a sum of said first and second leakage currents.

2. The integrated analog switch of claim 1, further comprising:

a hold circuit coupled to said body of said first semiconductor device, wherein said hold circuit pulls said body of said first semiconductor device towards a first voltage when said first semiconductor device is turned off; and

wherein said first current mirror circuit pulls said body of said second semiconductor device towards said first voltage when said second semiconductor device is turned off.

3. The integrated analog switch of claim 2, wherein:

said first current mirror circuit develops a voltage difference between an intermediate node and said body of said second semiconductor device when said second semiconductor device is turned off; and

wherein said hold circuit comprises;

a third semiconductor device coupled between a source voltage node and said intermediate node, wherein said third semiconductor device is turned on when said first semiconductor device is turned off; and

a fourth semiconductor device coupled between said intermediate node and said body of said first semiconductor device, wherein said fourth semiconductor device is turned on when said third semiconductor device is turned on, and wherein said fourth semiconductor device is sized to develop said voltage difference between said intermediate node and said body of said first semiconductor device when said first semiconductor device is turned off.

4. The integrated analog switch of claim 1, wherein said first current mirror circuit comprises:

a first half mirror circuit, coupled to said body of said second semiconductor device and to a first source voltage node, which develops a first mirror current proportional to said second leakage current; and

a second half mirror circuit, coupled to a second source voltage node, to said first half mirror circuit for sensing said first mirror current, and to said first switch terminal, which develops said first cancellation current proportional to said first mirror current and which applies said first cancellation current to said first switch terminal.

5. The integrated analog switch of claim 1, wherein said first leakage current is a multiple of said second leakage current and wherein said first current mirror circuit amplifies said second leakage current by said multiple plus one.

6. The integrated analog switch of claim 1, further comprising:

said first semiconductor device, when turned off, providing a third leakage current between said body of said first semiconductor device and said second switch terminal;

a third semiconductor device comprising first and second current terminals, a control terminal and a body, wherein said first current terminal of said third semiconductor device is coupled to said second switch terminal and wherein said second current terminal of said third semiconductor device is coupled to said body of said first semiconductor device;

wherein said third semiconductor device, when turned off, provides a fourth leakage current between said body of said third semiconductor device and said second switch terminal, wherein said fourth leakage current is proportional to said third leakage current; and

a second current mirror circuit, coupled to said second switch terminal and to said body of said third semiconductor device, which mirrors and amplifies said fourth leakage current to provide a second cancellation current applied to said second switch terminal, wherein said second cancellation current is equivalent to a sum of said third and fourth leakage currents.

7. The integrated analog switch of claim 6, wherein said third and fourth leakage are independent of each other providing independent cancellation of said first and third leakage currents of said first semiconductor device.

8. An integrated MOS switch, comprising:

a first MOS device having first and second current terminals coupled to first and second switch terminals, respectively, a control terminal receiving a first switch control signal, and a body, wherein said first MOS device provides a first leakage current between said body and said first switch terminal and a second leakage current between said body and said second switch terminal when said first MOS device is turned off by said first switch control signal;

a second MOS device having a first current terminal coupled to said first switch terminal, a second current terminal coupled to said body of said first MOS device, a control terminal receiving said first switch control signal, and a body, wherein said second MOS device provides a third leakage current between said body and said first switch terminal when said second MOS device is turned off by said first switch control signal;

a third MOS device having a first current terminal coupled to said second switch terminal, a second current terminal coupled to said body of said first MOS device, a control terminal receiving said first switch control signal, and a body, wherein said third MOS device provides a fourth leakage current between said body and said second switch terminal when said third MOS device is turned off by said first switch control signal;

a first hold circuit which holds said body of said first MOS device to a first voltage when said first MOS device is turned off by said first switch control signal;

a first mirror circuit which holds said body of said second MOS device to said first voltage when said second MOS device is turned off by said first switch control signal, and which applies a first cancellation current to said first switch terminal to cancel said first and third leakage currents based on mirroring and amplifying said third leakage current; and

a second mirror circuit which holds said body of said third MOS device to said first voltage when said third MOS device is turned off by said first switch control signal, and which applies a second cancellation current to said second switch terminal to cancel said second and fourth leakage currents based on mirroring and amplifying said fourth leakage current.

9. The integrated MOS switch of claim 8, wherein said first leakage current is a first multiple times said third leakage current, wherein said first mirror circuit amplifies said third leakage current by said first multiple plus one to provide said first cancellation current, wherein said second leakage current is a second multiple times said fourth leakage current, and wherein said second mirror circuit amplifies said fourth leakage current by said second multiple plus one to provide said second cancellation current.

10. The integrated MOS switch of claim 8, wherein said first, second, and third MOS devices comprise P-type MOS devices manufactured in a complementary MOS process that utilizes a single well substrate.

11. The integrated MOS switch of claim 8, wherein said first, second, and third MOS devices comprise N-type MOS devices manufactured in a complementary MOS process that utilizes a multiple well substrate.

12. The integrated MOS switch of claim 8, wherein said first hold circuit comprises:

a fourth MOS device having a first current terminal and a body coupled to a first source voltage node, a second current terminal coupled to an intermediate node, and a control terminal receiving a second switch control signal having an opposite logic state as said first switch control signal; and

a fifth MOS device having a first current terminal coupled to said intermediate node, a body coupled to said first source voltage node, and a control terminal and second current terminal coupled to said body of said first MOS device.

13. The integrated MOS switch of claim 12, wherein said first mirror circuit comprises:

a sixth MOS device having a first current terminal coupled to said intermediate node, a body coupled to said first source voltage node, and a control terminal and second current terminal coupled to said body of said second MOS device;

a seventh MOS device having a first current terminal coupled to said intermediate node, a body coupled to said first source voltage node, a control terminal coupled to said control terminal of said sixth MOS device, and a second current terminal;

an eighth MOS device having a first current terminal and a control terminal coupled to said second current terminal of said seventh MOS device, and a second current terminal and a body coupled to a second source voltage node; and

a ninth MOS device having a first current terminal coupled to said first switch terminal, a control terminal coupled to said control terminal of said eighth MOS device, and a second current terminal and a body coupled to said second source voltage node.

14. The integrated MOS switch of claim 13, wherein said second mirror circuit comprises:

a tenth MOS device having a first current terminal coupled to said intermediate node, a body coupled to said first source voltage node, and a control terminal and second current terminal coupled to said body of said third MOS device;

an eleventh MOS device having a first current terminal coupled to said intermediate node, a body coupled to said first source voltage node, a control terminal coupled to said control terminal of said tenth MOS device, and a second current terminal;

a twelfth MOS device having a first current terminal and a control terminal coupled to said second current terminal of said eleventh MOS device, and a second current terminal and a body coupled to said second source voltage node; and

a thirteenth MOS device having a first current terminal coupled to said second switch terminal, a control terminal coupled to said control terminal of said twelfth MOS device, and a second current terminal and body coupled to said second source voltage node.

15. The integrated MOS switch of claim 14, further comprising:

a fourteenth MOS device having a control terminal receiving said first switch control signal, a first current terminal coupled to said body of said second MOS device, and a second current terminal and a body coupled to said body of said first MOS device; and

a fifteenth MOS device having a control terminal receiving said first switch control signal, a first current terminal coupled to said body of said third MOS device, and a second current terminal and a body coupled to said body of said first MOS device.

16. The integrated MOS switch of claim 15, wherein:

said first leakage current of said first MOS device is a first multiple of said third leakage current of said second MOS device, and wherein sizes of said sixth, seventh, eighth, and ninth MOS devices of said first mirror circuit are selected to amplify said third leakage current by said first multiple plus one to provide said first cancellation current; and

wherein said second leakage current of said first MOS device is a second multiple of said fourth leakage current of said third MOS device, and wherein sizes of said tenth, eleventh, twelfth, and thirteenth MOS devices of said second mirror circuit are selected to amplify said fourth leakage current by said second multiple plus one to provide said second cancellation current.

17. The integrated MOS switch of claim 15, wherein said sixth and tenth MOS devices have approximately the same size to hold said bodies of said second and third MOS devices to said first voltage when said second and third MOS devices are turned off, and wherein a size of said fifth MOS device is selected to hold said body of said first device to said first voltage when said first MOS device is turned off.

18. The integrated MOS switch of claim 8, further comprising:

a fourth MOS device having first and second current terminals coupled to first and second switch terminals, respectively, a control terminal receiving a second switch control signal having an opposite logic state as said first switch control signal, and having a body, wherein said fourth MOS device provides a fifth leakage current between said body of said fourth MOS device and said first switch terminal and a sixth leakage current between said body of said fourth MOS device and said second switch terminal when said fourth MOS device is turned off by said second switch control signal;

a fifth MOS device having a first current terminal coupled to said first switch terminal, a second current terminal coupled to said body of said fourth MOS device, a control terminal receiving said second switch control signal, and a body, wherein said fifth MOS device provides a seventh leakage current between said body of said fifth MOS device and said first switch terminal when said fifth MOS device is turned off by said second switch control signal;

a sixth MOS device having a first current terminal coupled to said second switch terminal, a second current terminal coupled to said body of said fourth MOS device, a control terminal receiving said second switch control signal, and a body, wherein said sixth MOS device provides an eighth leakage current between said body of said sixth MOS device and said second switch terminal when said sixth MOS device is turned off by said second switch control signal;

a second hold circuit which holds said body of said fourth MOS device to a second voltage when said fourth MOS device is turned off by said second switch control signal;

a third mirror circuit which holds said body of said fifth MOS device to said second voltage when said fifth MOS device is turned off by said second switch control signal, and which applies a third cancellation current to said first switch terminal to cancel said fifth and seventh leakage currents based on mirroring and amplifying said seventh leakage current; and

a fourth mirror circuit which holds said body of said sixth MOS device to said second voltage when said sixth MOS device is turned off by said second switch control signal, and which applies a fourth cancellation current to said second switch terminal to cancel said sixth and eighth leakage currents based on mirroring and amplifying said sixth leakage current.

19. A method of canceling a leakage current of an integrated analog switch, wherein the integrated analog switch comprises a first semiconductor device having first and second current terminals coupled to first and second switch terminals, respectively, a body and a control terminal receiving a switch control signal, wherein the leakage current is developed through the body and the first current terminal when the first semiconductor switch device is turned off and when the body is pulled to a bias voltage level, said method comprising:

providing a second semiconductor device being a reduced-size replica of the first semiconductor device, wherein the second semiconductor device has first and second current terminals, a control terminal and a body;

providing the switch control signal to the control terminal of the second semiconductor device;

coupling the first current terminal of the second semiconductor device to the first current terminal of the first semiconductor device and coupling the second current terminal of the second semiconductor device to the body of the first semiconductor device;

pulling the body of the second semiconductor device to the bias voltage level when the first and second semiconductor devices are both turned off by the switch control signal, wherein the second semiconductor device develops a proportional current between the first current terminal and body of the second semiconductor device and wherein the proportional current is proportional to the leakage current of the first semiconductor device;

mirroring and amplifying the proportional current to provide a cancellation current; and

applying the cancellation current to the first switch terminal.

20. The method of claim 19, wherein said pulling comprises:

providing a third semiconductor device coupled to the body of the first semiconductor device; and

providing a fourth semiconductor device coupled to the body of the second semiconductor device and having a size selected for pulling the body of the second semiconductor device to the bias voltage level when the second semiconductor device is turned off.

21. The method of claim 19, wherein said amplifying comprises amplifying the proportional current so that the cancellation current is equivalent to a sum of the leakage current of the first semiconductor device and the proportional current of the second semiconductor device.