Self-adaptive and self-calibrated multiple-level non-volatile memories

• US 7,729,165 B2
• Filed: 03/29/2007
• Issued: 06/01/2010
• Est. Priority Date: 03/29/2007
• Status: Active Grant

• Current Assignee: Pegasus Semiconductor (Beijing) Co., Ltd.
• Original Assignee: Flashsilicon, Incorporation
• Inventors: Wang, Lee
• Primary Examiner(s): TRAN, MICHAEL THANH
• Application Number:
  US11/693,610
• Publication Number:
  US 20080239820A1
• Time in Patent Office: 1,160 Days
• Field of Search: 365/185.03, 365/185.24
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: G11C 2211/5634 Reference cells
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

Innovative self-adaptive and self-calibrated methods and structures for Multi-Level Cell (MLC) Non-Volatile Memory (NVM) are disclosed. In the MLC NVM, NVM cells are self-adaptively programmed into a fixed response tolerance window centered at the reference current or voltage corresponding to a selected level gate voltage applied to the controlled gates of NVM cells. The fixed response tolerance window is related to the threshold voltage tolerance window through the sense circuit gain. Properly choosing the sense circuit gain and the response window can control the threshold voltage tolerance window to a desired value. An incremental gate voltage larger than the threshold voltage tolerance window of each NVM cell will guarantee that each NVM cell will produce the correct output current (voltage) in response to applying to the control gate of the NVM cell the stepped voltage corresponding to the level of information stored in the NVM cell. As the stepped voltage applied to the gate of an NVM cell transitions from a voltage just below the threshold voltage of the NVM cell to a voltage corresponding to the threshold voltage of the NVM cell, the output current (voltage) from the NVM cell will pass the current (voltage) transition in comparison with the reference current (voltage). The current (voltage) transition can be detected and converted into the bit-word information representing the voltage level stored in the NVM cell. When the response of an NVM cell falls outside the response tolerance window into the guard-band regions, the NVM cell can be re-calibrated and the bit-word information can be saved from fading away.

Claims

1. A method of adjusting the threshold voltage of a nonvolatile memory cell having a floating gate or dielectric for receipt and storage of charge and a control gate, the method comprising:

placing a selected amount of charge on said floating gate or dielectric, said selected amount of charge corresponding to a desired threshold voltage for said non-volatile memory cell;

comparing a first output current and a second output current from the memory cell to a first reference current and a second reference current, when a first control voltage and a second control voltage are placed on said control gate, respectively, the first and second control voltages being within a selected range that includes said desired threshold voltage, the first control voltage being greater than said desired threshold voltage and the second control voltage being less than said desired threshold voltage; and

adjusting the charge on said floating gate or dielectric, when said first output current exceeds said first reference current, or when said second output current is less than said second reference current.

2. The method of claim 1 wherein the adjusting of the charge on said floating gate or dielectric comprises:

placing additional charge on the floating gate or dielectric to bring said second output current from the nonvolatile memory cell to being equal or greater than said second reference current.

3. The method of claim 1 wherein the readjusting of the charge on the floating gate or dielectric comprises:

reducing the charge on the floating gate or dielectric to bring said first output current from the nonvolatile memory cell to being less than or equal said first reference current.

4. Structure for adjusting the threshold voltage of a nonvolatile memory cell having a floating gate or dielectric for receipt and storage of charge and a control gate, the structure comprising:

means for placing a selected amount charge on said floating gate or dielectric, said selected amount of charge corresponding to a desired threshold voltage for said non-volatile memory cell;

means for comparing a first output current and a second output current from the memory cell to a first reference current and a second reference current, when a first control voltage and a second control voltage are placed on said control gate, respectively, the first and second control voltages being within a selected range that includes said desired threshold voltage, the first control voltage being greater than said desired threshold voltage and the second control voltage being less than said desired threshold voltage; and

means for adjusting the charge on said floating gate or dielectric, when said first output current exceeds said first reference current, or when said second output current is less than said second reference current.

5. The structure of claim 4 wherein the means for adjusting the charge on said floating gate or dielectric comprises:

means for placing additional charge on said floating gate or dielectric to bring said second output current from the nonvolatile memory cell to being equal or greater than said second reference current.

6. The structure of claim 4 wherein the means for adjusting the charge on said floating gate or dielectric comprises:

means for reducing the charge on said floating gate or dielectric to bring said first output current from the nonvolatile memory cell to being equal or less than said first reference current.

7. Structure comprising:

an array of nonvolatile memory cells, each nonvolatile memory cell having a floating gate or dielectric for receipt and storage of charge and a control gate;

means for placing a selected amount of charge on the floating gate or dielectric of a selected non-volatile memory cell in the array, said selected amount of charge corresponding to a desired threshold voltage for said selected non-volatile memory cell;

means for comparing a first output current and a second output current from said selected non-volatile memory cell to a first reference current and a second reference current, when a first control voltage and a second control voltage are placed on said control gate, respectively, the first and second control voltages being within a selected range that includes said desired threshold voltage, the first control voltage being greater than said desired threshold voltage and the second control voltage being less than said desired threshold voltage; and

means for adjusting the charge on the floating gate or dielectric of said selected non-volatile memory cell, when said first output current exceeds said first reference current, or when said second output current is less than said second reference current.

8. The structure of claim 7 wherein the means for adjusting the charge on the floating gate comprises:

means for placing additional charge on the floating gate or dielectric to bring said second output current from said selected nonvolatile memory cell to being equal or greater than said second reference current.

9. The structure of claim 7 wherein the means for adjusting the charge on the floating gate comprises:

means for reducing the charge on the floating gate or dielectric to bring said first output current from said selected nonvolatile memory cell to being equal or less than said first reference current.

10. The structure of claim 7 further comprising:

means for adding to the charge on the floating gate or dielectric of one or more nonvolatile memory cells in the array should the threshold voltage of said one or more nonvolatile memory cells drop beneath a minimum desired value.

11. A structure comprising:

an array of nonvolatile memory cells arranged in M rows and N columns, each cell in the array being capable of storing any one of a plurality of selected amounts of charge;

a voltage source for applying in sequence a plurality of selected voltages to row m, where m is an integer given by 1≦

m≦

M, thereby to store charge in selected ones of the nonvolatile memory cells in said row;

logic circuitry for preventing nonvolatile memory cells in row m not selected to receive said selected voltages from having their stored charge altered as said selected voltages are applied to row m; and

circuitry for restoring a desired amount of charge on any one of the memory cells in row m should the charge on said memory cell be reduced;

said structure further comprising;

means for causing said voltage source to initially apply voltage increments of a first magnitude to row m and once the charge stored in one or more selected nonvolatile memory cells reaches a certain magnitude, to apply voltage increments of a second magnitude to row m until the desired charge is achieved on the one or more selected nonvolatile memory cells, the second magnitude being smaller than the first magnitude.