Low current microcontroller circuit

• US 7,729,205 B2
• Filed: 03/03/2008
• Issued: 06/01/2010
• Est. Priority Date: 07/11/2002
• Status: Expired due to Fees

• Current Assignee: Action Manufacturing LLC
• Original Assignee: Action Manufacturing LLC
• Inventors: Siebott, Jonathan C., Frantz, Richard A.
• Primary Examiner(s): Miska; Vit W
• Application Number:
  US12/041,434
• Publication Number:
  US 20090022012A1
• Time in Patent Office: 820 Days
• Field of Search: 368/10, 368/11, 368107-110, 368/113, 368118-119, 368/155, 368/156, 368200-202, 331/18, 331/46, 331/49, 331/55, 331/56, 331/145, 331/150, 331/53, 331/154, 331/158, 331/160, 331172-173, 102/215, 102/276
• US Class Current: 368/10
• CPC Class Codes: G06F 1/14 Time supervision arrangements, e.g. real time clock
• CPC Class Codes: G06F 1/3228 Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: H01M 6/40 Printed batteries , e.g. thin film batteries
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method and system for accurate timing in a low current system useful in fuzing applications generates a first count of oscillations of an oscillator of unknown frequency during a first period of unknown duration. A second count of oscillations of the oscillator is generated during a second period of a known duration. The duration of the first period is calculated based on the first count and the second count. A solid-state, thin-film battery is able to be used by virtue of low-current characteristics of the system, enabling extended shelf life for fuzing systems.

Claims

1. A computer-implemented method performed by one or more processors for determining a duration of a first period beginning from a startup time in a system including a first oscillator of an unknown frequency and a second oscillator of a known frequency, the method comprising performing the following by operation of one or more processors:

generating a first count corresponding to a number of oscillations of the first oscillator during the first period;

generating a second count corresponding to a number of oscillations of the first oscillator during a second period, the second period having a duration corresponding to a known number of oscillations of the second oscillator;

converting the first count to an equivalent number of oscillations of the second oscillator during the first period;

calculating the duration of the first period based on the converted number of oscillations of the second oscillator and the known frequency of the second oscillator; and

calculating a system time since the startup time using the calculated duration of the first period.

2. The method of claim 1 further comprising generating an interrupt to indicate oscillation of the second oscillator, wherein the second period occurs after the interrupt.

3. A timing system comprising:

a first oscillator;

a second oscillator;

a first means for counting a number of oscillations of the second oscillator during a first period beginning at a startup time;

a second means for counting a number of oscillations of the second oscillator during a second period beginning after oscillation of the first oscillator; and

a processor for generating a time value corresponding to the first period based at least in part on the number of oscillations of the second oscillator during the first period and the number of oscillations of the second oscillator during the second period, wherein the time value corresponds to the startup delay of the first oscillator, the processor further operable to calculate a system time since the startup time using the time value corresponding to the startup delay.

4. The timing system of claim 3 wherein the first oscillator comprises a crystal oscillator.

5. The timing system of claim 3 wherein the second oscillator comprises a RC oscillator.

6. The timing system of claim 3 further comprising a controller operable to correct for the startup delay of the first oscillator.

7. The timing system of claim 3, wherein the timing system comprises a shelf life greater than twenty years and is operable at temperatures down to −

45.6°

C.

8. A timing system comprising:

a first crystal oscillator;

a second oscillator, wherein a frequency of the second oscillator is unknown;

a first counter coupled to the second oscillator, the first counter generating a first count corresponding to a number of oscillations of the second oscillator during a first period beginning at a startup time and generating a second count corresponding to a number of oscillations of the second oscillator during a second period of a known number of oscillations of the first crystal oscillator;

a processor coupled to the first counter for receiving the first count and the second count and generating a time value corresponding to the first period based on the first count and the second count, wherein the time value corresponds to a startup delay of the first crystal oscillator, the processor further operable to calculate a system time since the startup time using the time value corresponding to the startup delay.

9. The timing system of claim 8 wherein the timing system is operable to correct for the startup delay of the first crystal oscillator.

10. The timing system of claim 8 further comprising a controller, the controller operable to update the first counter to adjust for the startup delay of the first crystal oscillator.

11. The timing system of claim 8, wherein the timing system comprises a shelf life greater than twenty years and is operable at temperatures down to −

45.6°

C.

12. The timing system of claim 8 wherein the second oscillator comprises a RC oscillator.

13. The timing system of claim 8 wherein the first counter is operable to generate a third count, and wherein a controller generates a firing signal based on the third count.