Switching device

• US 7,729,258 B2
• Filed: 05/29/2007
• Issued: 06/01/2010
• Est. Priority Date: 05/30/2006
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Andou, Masamichi, Date, Hisakazu, Ezawa, Masatoshi
• Primary Examiner(s): Pham; Chi H
• Assistant Examiner(s): LOPATA, ROBERT J
• Application Number:
  US11/754,960
• Publication Number:
  US 20070280278A1
• Time in Patent Office: 1,099 Days
• Field of Search: 370/235, 370/422, 370/389, 370/468, 370/229
• US Class Current: 370/235
• CPC Class Codes: H04L 47/10 Flow control; Congestion control
• CPC Class Codes: H04L 47/30 in combination with information about buffer occupancy at either end or at transit nodes
• CPC Class Codes: H04L 49/254 Centralised controller, i.e. arbitration or scheduling
• CPC Class Codes: H04L 49/3018 Input queuing
• CPC Class Codes: H04L 49/3027 Output queuing
• CPC Class Codes: H04L 49/506 Backpressure

Abstract

A multiport switch circuit which performs transfer according to flow control and a protocol with an ordering rule specified, wherein the circuit for avoiding packets from clogging is realized in a small size. A packet receiving side circuit has a packet selection output circuit to suppress a circuit size by decreasing the number of transfer data paths, and the packet selection output circuit performs output of selected packets according to a priority packet type selection instruction signal in addition to output of a receiving order packet according to a receiving order output instruction signal to make it possible to avoid clogging caused because the packets made to wait for transmission by the flow control cannot be overtaken by another packet type according to the ordering rule.

Claims

1. A switching device for switching packets having a plurality of packet types to a plurality of devices according to a PCI Express protocol, the switching device comprising:

a receiver adapted to receive packets inputted into the switching device, the receiver having a buffer; and

a transmitter adapted to transmit packets to a first device in the plurality of devices, the transmitter having a buffer provided for each packet type;

when a remaining capacity of a first transmitter buffer which stores a first packet type becomes insufficient, the transmitter transmits to the receiver a first signal indicating that the remaining capacity of the first transmitter buffer has become insufficient,

when the receiver receives the first signal, the receiver transmits packets to the transmitter which are not of the first packet type according to a receiving order of the packets, and

when the receiver does not receive the first signal, the receiver transmits the packets to the transmitter according to the receiving order.

2. The switching device according to claim 1, further comprising:

a receiver memory,

a receiving order management unit for storing the receiving order of the packets,

a priority packet type selection circuit,

a packet selection output circuit, and

a packet type instruction circuit, wherein

the receiver memory performs a first-in first-out operation of the packets for each of the packet types according to the receiving order,

the priority packet type selection circuit selects and outputs packets from the receiver memory according to packet type,

when the priority packet type selection circuit receives the first signal, the priority packet type selection circuit transmits a second signal for prohibiting transfer of packets of the first packet type to the packet type instruction circuit,

the receiving order management unit transmits to the packet type instruction circuit a third signal indicating a packet type to be transferred according to the receiving order,

when the packet type instruction circuit receives the second signal, the packet type instruction circuit determines a packet type corresponding to a packet which is other than the first packet type and which has arrived first according to the second signal and the third signal, and transmits a fourth signal indicating the determined packet type to the packet selection output circuit, and

when the packet selection output circuit receives the fourth signal, the packet type selection circuit selects and transfers the packet of the determined packet type indicated by the fourth signal from the receiver memory.

3. The switching device according to claim 2, wherein

if the packet type instruction circuit does not receive the second signal, the packet type instruction circuit determines the packet type corresponding to the first-arrived packet according to the third signal and transmits the fourth signal indicating the determined packet type to the packet selection output circuit.

7. The switching device according to claim 1, wherein one of the packet types is one of Posted indicating a write request, NonPosted indicating a read request, and Completion indicating a reply to a read request.

8. The switching device according to claim 1, wherein one of the devices is one of a storage medium control device, an image processing control device, and a communication control device.

4. A switching device for switching packets having a plurality of packet types to a plurality of devices according to a PCI Express protocol, wherein

the plurality of devices each has a receiver memory adapted to store packets,

when a remaining capacity of the receiver memory of a first device with respect to a first packet type the packet types becomes insufficient, the first device transmits to a switching device a first signal indicating that the remaining capacity of the receiver memory with respect to individual packet types has become insufficient,

when the switching device receives the first signal, the switching device transfers packets which have destinations other than the first device according to a packet receiving order, and

when the switching device does not receive the first signal, the switching device transfers individual packets according to the packet receiving order.

5. The switching device according to claim 4, comprising:

a receiver memory,

a transmission packet type management unit for storing the packet receiving order and destinations of individual packets, and

a packet selection output circuit, wherein

when the transmission packet type management unit receives a first signal, the transmission packet type management unit transmits to the packet selection output circuit a second signal indicating a packet which is a destination other than the first device and corresponds to a first-arrived packet according to the receiving order and the destination, and

when the packet selection output circuit receives the second signal, the packet type selection circuit selects and transfers a packet indicated by the second signal from the receiver memory.

6. The switching device according to claim 5, wherein

when the packet type instruction circuit does not receive the second signal, packet corresponding to the first-arrived packet is transmitted to the packet selection output circuit according to the packet receiving order.